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november 1993 order number: 270500-008 m80c186 chmos high integration 16-bit microprocessor military y operation modes include: e enhanced mode which has e dram refresh e power-save logic e direct interface to new cmos numerics coprocessor e compatible mode e nmos m80186 pin-for-pin replacement for non-numerics applications y integrated feature set e enhanced m80c86/c88 cpu e clock generator e 2 independent dma channels e programmable interrupt controller e 3 programmable 16-bit timers e dynamic ram refresh control unit e programmable memory and peripheral chip select logic e programmable wait state generator e local bus controller e power save logic e system-level testing support (high impedance test mode) y available in 10 mhz and 12.5 mhz versions y direct addressing capability to 1 mbyte and 64 kbyte i/o y completely object code compatible with all existing m8086/m8088 software and also has 10 additional instructions over m8086/m8088 y complete system development support e all m8086 and nmos m80186 software development tools can be used for m80c186 system development e assembler, pl/m, pascal, fortran, and system utilities e in-circuit-emulator (ice tm -c186) y available in 68-pin ceramic pin grid array (pga) and 68-lead ceramic quad flat pack (see packaging outlines and dimensions, order y 231369) y available in two product grades: e mil-std-883, b 55 cto a 125 c(t c ) e military temperature only (mto), b 55 cto a 125 c(t c ) the intel m80c186 is a chmos high integration microprocessor. it has features which are new to the m80186 family which include a dram refresh control unit, power-save mode and a direct numerics interface. when used in ``compatible'' mode, the m80c186 is 100% pin-for-pin compatible with the nmos m80186 (except for m8087 applications). the ``enhanced'' mode of operation allows the full feature set of the m80c186 to be used. the m80c186 is upward compatible with m8086 and m8088 software and fully compatible with m80186 and m80188 software. 270500 1 figure 1. m80c186 block diagram
m80c186 pin grid array 270500 30 quad flat pack 270500 31 figure 2. m80c186 pinout diagram for additional packaging information refer to ``packaging outlines and dimensions'', order number 231369 2
m80c186 table 1. m80c186 pin description symbol pga qfp type name and function v cc ,v cc 9, 43 1, 35 i system power: a 5 volt power supply. v ss ,v ss 26, 60 52, 18 i system ground. reset 57 21 o reset output indicates that the m80c186 cpu is being reset, and can be used as a system reset. it is active high, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the res signal. reset goes inactive 2 clockout periods after res goes inactive. when tied to the test /busy pin, reset forces the m80c186 into enhanced mode. x1, x2 59, 58 19, 20 i crystal inputs x1 and x2 provide external connections for a fundamental mode or third overtone parallel resonant crystal for the internal oscillator. x1 can connect to an external clock instead of a crystal. in this case, minimize the capacitance on x2 or drive x2 with complemented x1. the input or oscillator frequency is internally divided by two to generate the clock signal (clkout). clkout 56 22 o clock output provides the system with a 50% duty cycle waveform. all device pin timings are specified relative to clkout. clkout has sufficient mos drive capabilities for the numeric processor extension. res 24 54 i system reset causes the m80c186 to immediately terminate its present activity, clear the internal logic, and enter a dormant state. this signal may be asynchronous to the m80c186 clock. the m80c186 begins fetching instructions approximately 7 clock cycles after res is returned high. for proper initialization, v cc must be within specifications and the clock signal must be stable for more than 4 clocks with res held low. res is internally synchronized. this input is provided with a schmitt-trigger to facilitate power-on res generation via an rc network. when res occurs, the m80c186 will drive the status lines to an inactive level for one clock, and then float them. test /busy 47 31 i the test pin is sampled during and after reset to determine whether the m80c186 is to enter compatible or enhanced mode. enhanced mode requires test to be high on the rising edge of res and low four clocks later. any other combination will place the m80c186 in compatible mode. a weak internal pullup insures a high state when the pin is not driven. test ein compatible mode this pin is configured to operate as test . this pin is examined by the wait instruction. if the test input is high when wait execution begins, instruction execution will suspend. test will be resampled every five clocks until it goes low, at which time execution will resume. if interrupts are enabled while the m80c186 is waiting for test , interrupts will be serviced. busyein enhanced mode, this pin is configured to operate as busy. the busy input is used to notify the m80c186 of numerics processor extension activity. floating point instructions executing in the m80c186 sample the busy pin to determine when the numerics processor is ready to accept a new command. busy is active high. 3
m80c186 table 1. m80c186 pin description (continued) symbol pga qfp type name and function tmr in 1 tmr in 0, 20 21 58 57 i i timer inputs are used either as clock or control signals, depending upon the programmed timer mode. these inputs are active high (or low-to-high transitions are counted) and internally synchronized. tmr out 0, tmr out 1 23 22 56 55 o o timer outputs are used to provide single pulse or continous waveform generation, depending upon the timer mode selected. drq1 drq0 18 19 59 60 i i dma request is driven high by an external device when it desires that a dma channel (channel 0 or 1) perform a transfer. these signals are active high, level-triggered, and internally synchronized. nmi 46 32 i non-maskable interrupt is an edge-triggered input which causes a type 2 interrupt. nmi is not maskable internally. a transition from a low to high initiates the interrupt at the next instruction boundary. nmi is latched internally. an nmi duration of one clock or more will guarantee service. this input is internally synchronized. int0, int1 int3/inta1 int2/inta0 45, 44 41 42 33, 34 37 36 i/o i/o i maskable interrupt requests can be requested by activating one of these pins. when configured as inputs, these pins are active high. interrupt requests are synchronized internally. int2 and int3 may be configured via software to provide active-low interrupt-acknowledge output signals. all interrupt inputs may be configured via software to be either edge- or level-triggered. to ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. when slave mode is selected, the function of these pins changes (see interrupt controller section of this data sheet). a19/s6, a16/s3 a17/s4, a18/s5, 65 68 67 66 13 10 11 12 o o o o address bus outputs (16 19) and bus cycle status (3 6) reflect the four most significant address bits during t 1 . these signals are active high. during t 2 ,t 3 ,t w , and t 4 , status information is available on these lines as encoded below: low high s6 processor cycle dma cycle s3, s4, and s5 are defined as low during t 2 t 4 . ad15 1 9 i/o address/data bus (0 15) signals constitute the time multiplexed memory or i/o address (t 1 ) and data (t 2 ,t 3 ,t w , ad14 3 7 and t 4 ) bus. the ad13 5 5 ad12 7 3 bus is active high. a 0 is analogous to bhe for the lower byte of the data bus, pins d 7 through d 0 . it is low during t 1 when ad11 10 68 a byte is to be transferred onto the lower portion of the bus in ad10 12 66 memory or i/o operations. ad9 14 64 ad8 16 62 ad7 2 8 ad6 4 6 ad5 6 4 ad4 8 2 ad3 11 67 ad2 13 65 ad1 15 63 ad0 17 61 4
m80c186 table 1. m80c186 pin description (continued) symbol pga qfp type name and function bhe 64 14 o the bhe (bus high enable) signal is analogous to a0 in that it is used to enable data on to the most significant half of the data bus, pins d15 d8. bhe will be low during t 1 when the upper byte is transferred and will remain low through t 3 and t w . bhe does not need to be latched. bhe will float during hold. in enhanced mode, bhe will also be used to signify dram refresh cycles. a refresh cycle is indicated by bhe and a0 being high. bhe and a0 encodings bhe value a0 value function 0 0 word transfer 0 1 byte transfer on upper half of data bus (d15 d8) 1 0 byte transfer on lower half of data bus (d 7 d 0 ) 1 1 refresh ale/qs0 61 17 o address latch enable/queue status 0 is provided by the m80c186 to latch the address. ale is active high. addresses are guaranteed to be valid on the trailing edge of ale. the ale rising edge is generated off the rising edge of the clkout immediately preceding t 1 of the associated bus cycle, effectively one-half clock cycle earlier than in the standard m8086. the trailing edge is generated off the clkout rising edge in t 1 as in the m8086. note that ale is never floated. wr /qs1 63 15 o write strobe/queue status 1 indicates that the data on the bus is to be written into a memory or an i/o device. wr is active for t 2 ,t 3 , and t w of any write cycle. it is active low, and floats during ``hold.'' it is driven high for one clock during reset, and then floated. when the m80c186 is in queue status mode, the ale/qs0 and wr /qs1 pins provide information about processor/instruction queue interaction. qs1 qs0 queue operation 0 0 no queue operation 0 1 first opcode byte fetched from the queue 1 1 subsequent byte fetched from the queue 1 0 empty the queue rd /qsmd 62 16 o read strobe indicates that the m80c186 is performing a memory or i/o read cycle. rd is active low for t 2 ,t 3 , and t w of any read cycle. it is guaranteed not to go low in t 2 until after the address bus is floated. rd is active low, and floats during ``hold''. rd is driven high for one clock during reset, and then the output driver is floated. a weak internal pull-up mechanism of the rd line holds it high when the line is not driven. during reset the pin is sampled to determine whether the m80c186 should provide ale, wr and rd , or if the queue-status should be provided. rd should be connected to gnd to provide queue-status data. 5
m80c186 table 1. m80c186 pin description (continued) symbol pga qfp type name and function ardy 55 23 i asynchronous ready informs the m80c186 that the addressed memory space or i/o device will complete a data transfer. the ardy input pin will accept an asynchronous input, and is active high. only the rising edge is internally synchronized by the m80c186. this means that the falling edge of ardy must be synchronized to the m80c186 clock. if connected to v cc , no wait states are inserted. asynchronous ready (ardy) or synchronous ready (srdy) must be active to terminate a bus cycle. if unused, this line should be tied low to yield control to the srdy pin. srdy 49 29 i synchronous ready must be synchronized externally to the m80c186. the use of srdy provides a relaxed system-timing specification on the ready input. this is accomplished by eliminating the one-half clock cycle which is required for internally resolving the signal level when using the ardy input. this line is active high. if this line is connected to v cc , no wait states are inserted. asynchronous ready (ardy) or synchronous ready (srdy) must be active before a bus cycle is terminated. if unused, this line should be tied low to yield control to the ardy pin. lock 48 30 o lock output indicates that other system bus masters are not to gain control of the system bus while lock is active low. the lock signal is requested by the lock prefix instruction and is activated at the beginning of the first data cycle associated with the instruction following the lock prefix. it remains active until the completion of the instruction following the lock prefix. no prefetches will occur while lock is asserted. lock is active low, is driven high for one clock during reset, and then floated. s0 ,s1 ,s2 52, 53, 54 26, 25, 24 o bus cycle status s0 s2 are encoded to provide bus- transaction information: m80c186 bus cycle status information s2 s1 s0 bus cycle initiated 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 passive (no bus cycle) the status pins float during hold/hlda. s2 may be used as a logical m/io indicator, and s1 as a dt/r indicator. the status lines are driven high for one clock during reset, and then floated until a bus cycle begins. 6
m80c186 table 1. m80c186 pin description (continued) symbol pga qfp type name and function hlda (output) hold (input) 51 50 27 28 o i hold indicates that another bus master is requesting the local bus. the hold input is active high. hold may be asynchronous with respect to the m80c186 clock. the m80c186 will issue a hlda (high) in response to a hold request at the end of t 4 or t i . simultaneous with the issuance of hlda, the m80c186 will float the local bus and control lines. after hold is detected as being low, the m80c186 will lower hlda. when the m80c186 needs to run another bus cycle, it will again drive the local bus and control lines. in enhanced mode, hlda will go low when a dram refresh cycle is pending in the m80c186 and an external bus master has control of the bus. it will be up to the external master to relinquish the bus by lowering hold so that the m80c186 may execute the refresh cycle. lowering hold for four clocks and returning high will insure only one refresh cycle to the external master. hlda will immediately go active after the refresh cycle has taken place. ucs 34 44 o upper memory chip select is an active low output whenever a memory reference is made to the defined upper portion (1k 256k block) of memory. this line is not floated during bus hold. the address range activating ucs is software programmable. ucs and lcs are sampled upon the rising edge of res .if both pins are held low, the m80c186 will enter once mode. in once mode all pins assume a high impedance state and remain so until a subsequent reset. ucs has a weak internal pullup for normal operation. lcs 33 45 o lower memory chip select is active low whenever a memory reference is made to the defined lower portion (1k 256k) of memory. this line is not floated during bus hold. the address range activating lcs is software programmable. ucs and lcs are sampled upon the rising edge of res .if both pins are held low, the m80c186 will enter once mode. in once mode all pins assume a high impedance state and remain so until a subsequent reset. ucs has a weak internal pullup for normal operation. mcs0 /pereq 38 40 i/o mid-range memory chip select signals are active low mcs1 /error 37 41 i/o when a memory reference is made to the defined mid- mcs2 36 42 o range portion of memory (8k 512k). these lines are not mcs3 /nps 35 43 o floated during bus hold. the address ranges activating mcs0 3 are software programmable. in enhanced mode, mcs0 becomes a pereq input (processor extension request). when connected to the numerics processor extension, this input is used to signal the m80c186 when to make numeric data transfers to and from the npx. mcs3 becomes nps (numeric processor select) which may only be activated by communication to the numerics processor extension. mcs1 becomes error in enhanced mode and is used to signal numerics coprocessor errors. 7
m80c186 table 1. m80c186 pin description (continued) symbol pga qfp type name and function pcs0 pcs1 4 27, 28, 29, 30 25 51, 50, 49, 48 53 o o peripheral chip select signals 0 4 are active low when a reference is made to the defined peripheral area (64k byte i/o space). these lines are not floated during bus hold. the address ranges activating pcs0 4 are software programmable. pcs5 /a1 31 47 o peripheral chip select 5 or latched a1 may be programmed to provide a sixth peripheral chip select, or to provide an internally latched a1 signal. the address range activating pcs5 is software programmable. when programmed to provide latched. a1, rather than pcs5 , this pin will retain the previously latched value of a1 during a bus hold. a1 is active high. pcs6 /a2 32 46 o peripheral chip select 6 or latched a2 may be programmed to provide a seventh peripheral chip select, or to provide an internally latched a2 signal. the address range activating pcs6 is software programmable. when programmed to provide latched a2, rather than pcs6 , this pin will retain the previously latched value of a2 during a bus hold. a2 is active high. dt/r 40 38 o data transmit/receive controls the direction of data flow through the external m8286/m8287 data bus transceiver. when low, data is transferred to the m80c186. when high the m80c186 places write data on the data bus. den 39 39 o data enable is provided as an m8286/m8287 data bus transceiver output enable. den is active low during each memory and i/o access. den is high whenever dt/r changes state. 8
m80c186 functional description introduction the following functional description describes the base architecture of the m80c186. this architecture is common to the m8086, m8088, m80186 and m80286 microprocessor families as well. the m80c186 is a very high integration 16-bit microproc- essor. it combines 15 20 of the most common mi- croprocessor system components onto one chip. the m80c186 is object code compatible with the m8086/m8088 microprocessors and adds 10 new instruction types to the existing m8086/m8088 in- struction set. the m80c186 has two major modes of operation, compatible and enhanced. in compatible mode the m80c186 is completely compatible with nmos m80186, with the exception of m8087 support. all pin functions, timings, and drive capabilities are identical. the enhanced mode adds three new fea- tures to the system design. these are power-save control, dynamic ram refresh, and an asynchro- nous numerics co-processor interface. m80c186 base architecture the m8086, m8088, m80186, and m80286 family all contain the same basic set of registers, instructions, and addressing modes. the m80c186 processor is upward compatible with the m8086, m8088, and m80286 cpus. register set the m80c186 base architecture has fourteen regis- ters as shown in figures 3a and 3b. these registers are grouped into the following categories. general registers eight 16-bit general purpose registers may be used to contain arithmetic and logical operands. four of these (ax, bx, cx, and dx) can be used as 16-bit registers or split into pairs of separate 8-bit registers. segment registers four 16-bit special purpose registers select, at any given time, the segments of memory that are imme- diately addressable for code, stack, and data. (for usage, refer to memory organization.) base and index registers four of the general purpose registers may also be used to determine offset addresses of operands in memory. these registers may contain base address- es or indexes to particular locations within a seg- ment. the addressing mode selects the specific reg- isters for operand and address calculations. status and control registers two 16-bit special purpose registers record or alter certain aspects of the m80c186 processor state. these are the instruction pointer register, which contains the offset address of the next sequential instruction to be executed, and the status word register, which contains status and control flag bits (see figures 3a and 3b). status word description the status word records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operation of the m80c186 within a given operating mode (bits 8, 9, and 10). the status word register is 16-bits wide. the function of the status word bits is shown in table 2. 9
m80c186 16-bit special register register name functions 7070 byte addressable ax ah al multiply/divide register (8-bit dx dh dl i/o instructions * shown) names cx ch cl ( loop/shift/repeat/count % bx bh bl base registers bp * si index registers di * sp ( stack pointer 15 0 general registers 15 0 cs code segment selector ds data segment selector ss stack segment selector es extra segment selector segment registers 15 0 f status word ip instruction pointer status and control registers figure 3a. m80c186 register set 270500 4 figure 3b. status word format 10
m80c186 table 2. status word bit functions bit name function position 0 cf carry flageset on high-order bit carry or borrow; cleared otherwise 2 pf parity flageset if low-order 8 bits of result contain an even number of 1-bits; cleared otherwise 4 af set on carry from or borrow to the low order four bits of al; cleared otherwise 6 zf zero flageset if result is zero; cleared otherwise 7 sf sign flageset equal to high- order bit of result (0 if positive, 1 if negative) 8 tf single step flageonce set, a single step interrupt occurs after the next instruction executes. tf is cleared by the single step interrupt. 9 if interrupt-enable flagewhen set, maskable interrupts will cause the cpu to transfer control to an interrupt vector specified location. 10 df direction flagecauses string instructions to auto decrement the appropriate index register when set. clearing df causes auto increment. 11 of overflow flageset if the signed result cannot be expressed within the number of bits in the destination operand; cleared otherwise instruction set the instruction set is divided into seven categories: data transfer, arithmetic, shift/rotate/logical, string manipulation, control transfer, high-level instruc- tions, and processor control. these categories are summarized in figure 4. an m80c186 instruction can reference anywhere from zero to several operands. an operand can re- side in a register, in the instruction itself, or in memo- ry. specific operand addressing modes are dis- cussed later in this data sheet. memory organization memory is organized in sets of segments. each seg- ment is a linear contiguous sequence of up to 64k (2 16 ) 8-bit bytes. memory is addressed using a two- component address (a pointer) that consists of a 16- bit base segment and a 16-bit offset. the 16-bit base values are contained in one of four internal segment register (code, data, stack, extra). the physical address is calculated by shifting the base value left by four bits and adding the 16-bit offset value to yield a 20-bit physical address (see figure 5). this allows fo r a 1 mbyte physical address size. all instructions that address operands in memory must specify the base segment and the 16-bit offset value. for speed and compact instruction encoding, the segment register used for physical address gen- eration is implied by the addressing mode used (see table 3). these rules follow the way programs are written (see figure 6) as independent modules that require areas for code and data, a stack, and access to external data areas. special segment override instruction prefixes allow the implicit segment register selection rules to be overridden for special cases. the stack, data, and extra segments may coincide for simple programs. 11
m80c186 general purpose mov move byte or word push push word onto stack pop pop word off stack pusha push all registers on stack popa pop all registers from stack xchg exchange byte or word xlat translate byte input/output in input byte or word out output byte or word address object lea load effective address lds load pointer using ds les load pointer using es flag transfer lahf load ah register from flags sahf store ah register in flags pushf push flags onto stack popf pop flags off stack addition add add byte or word adc add byte or word with carry inc increment byte or word by 1 aaa ascii adjust for addition daa decimal adjust for addition subtraction sub subtract byte or word sbb subtract byte or word with borrow dec decrement byte or word by 1 neg negate byte or word cmp compare byte or word aas ascii adjust for subtraction das decimal adjust for subtraction multiplication mul multiply byte or word unsigned imul integer multiply byte or word aam ascii adjust for multiply ascii division div divide byte or word unsigned idiv integer divide byte or word aad ascii adjust for division cbw convert byte to word cwd convert word to doubleword movs move byte or word string ins input bytes or word string outs output bytes or word string cmps compare byte or word string scas scan byte or word string lods load byte or word string stos store byte or word string rep repeat repe/repz repeat while equal/zero repne/repnz repeat while not equal/not zero logicals not ``not'' byte or word and ``and'' byte or word or ``inclusive or'' byte or word xor ``exclusive or'' byte or word test ``test'' byte or word shifts shl/sal shift logical/arithmetic left byte or word shr shift logical right byte or word sar shift arithmetic right byte or word rotates rol rotate left byte or word ror rotate right byte or word rcl rotate through carry left byte or word rcr rotate through carry right byte or word flag operations stc set carry flag clc clear carry flag cmc complement carry flag std set direction flag cld clear direction flag sti set interrupt enable flag cli clear interrupt enable flag external synchronization hlt halt until interrupt or reset wait wait for test pin active esc escape to extension processor lock lock bus during next instruction no operation nop no operation high level instructions enter format stack for procedure entry leave restore stack for procedure exit bound detects values outside prescribed range figure 4. m80c186 instruction set 12
m80c186 conditional transfers ja/jnbe jump if above/not below nor equal jae/jnb jump if above or equal/not below jb/jnae jump if below/not above nor equal jbe/jna jump if below or equal/not above jc jump if carry je/jz jump if equal/zero jg/jnle jump if greater/not less nor equal jge/jnl jump if greater or equal/not less jl/jnge jump if less/not greater nor equal jle/jng jump if less or equal/not greater jnc jump if not carry jne/jnz jump if not equal/not zero jno jump if not overflow jnp/jpo jump if not parity/parity odd jns jump if not sign jo jump if overflow jp/jpe jump if parity/parity even js jump if sign unconditional transfers call call procedure ret return from procedure jmp jump iteration controls loop loop loope/loopz loop if equal/zero loopne/loopnz loop if not equal/not zero jcxz jump if register cx e 0 interrupts int interrupt into interrupt if overflow iret interrupt return figure 4. m80c186 instruction set (continued) to access operands that do not reside in one of the four immediately available segments, a full 32-bit pointer can be used to reload both the base (seg- ment) and offset values. 270500 5 figure 5. two component address table 3. segment register selection rules memory segment implicit segment reference register selection rule needed used instructions code (cs) instruction prefetch and immediate data. stack stack (ss) all stack pushes and pops; any memory references which use bp register as a base register. external extra (es) all string instruction data references which use (global) the di register as an index. local data data (ds) all other data references. 270500 6 figure 6. segmented memory helps structure software 13
m80c186 addressing modes the m80c186 provides eight categories of address- ing modes to specify operands. two addressing modes are provided for instructions that operate on register or immediate operands: # register operand mode: the operand is located in one of the 8- or 16-bit general registers. # immediate operand mode: the operand is in- cluded in the instruction. six modes are provided to specify the location of an operand in a memory segment. a memory operand address consists of two 16-bit components: a seg- ment base and an offset. the segment base is sup- plied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix. the offset, also called the effective address, is calculated by summing any combination of the following three address ele- ments: # the displacement (an 8- or 16-bit immediate value contained in the instruction); # the base (contents of either the bx or bp base registers); and # the index (contents of either the si or di index registers). any carry out from the 16-bit addition is ignored. eight-bit displacements are sign extended to 16-bit values. combinations of these three address elements de- fine the six memory addressing modes, described below. # direct mode: the operand's offset is contained in the instruction as an 8- or 16-bit displacement el- ement. # register indirect mode: the operand's offset is in one of the registers si, di, bx, or bp. # based mode: the operand's offset is the sum of an 8- or 16-bit displacement and the contents of a base register (bx or bp). # indexed mode: the operand's offset is the sum of an 8- or 16-bit displacement and the contents of an index register (si or di). # based indexed mode: the operand's offset is the sum of the contents of a base register and an index register. # based indexed mode with displacement: the op- erand's offset is the sum of a base register's con- tents, an index register's contents, and an 8- or 16-bit displacement. data types the m80c186 directly supports the following data types: # integer: a signed binary numeric value contained in an 8-bit byte or a 16-bit word. all operations assume a 2's complement representation. signed 32- and 64-bit integers are supported us- ing a numeric data coprocessor with the m80c186. # ordinal: an unsigned binary numeric value con- tained in an 8-bit byte or a 16-bit word. # pointer: a 16- or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component in addition to a 16-bit offset compo- nent. # string: a contiguous sequence of bytes or words. a string may contain from 1 to 64k bytes. # ascii: a byte representation of alphanumeric and control characters using the ascii standard of character representation. # bcd: a byte (unpacked) representation of the decimal digits 0 9. # packed bcd: a byte (packed) representation of two decimal digits (0 9). one digit is stored in each nibble (4-bits) of the byte. # floating point: a signed 32-, 64-, or 80-bit real number representation. (floating point operands are supported using a numeric data coprocessor with the m80c186.) in general, individual data elements must fit within defined segment limits. figure 7 graphically repre- sents the data types supported by the m80c186. i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. separate instructions address the i/o space with either an 8-bit port address, specified in the in- struction, or a 16-bit port address in the dx register. 8-bit port addresses are zero extended such that a 15 a 8 are low. i/o port addresses 00f8(h) through 00ff(h) are reserved. interrupts an interrupt transfers execution to a new program location. the old program address (cs:ip) and ma- chine state (status word) are saved on the stack to allow resumption of the interrupted program. inter- rupts fall into three classes: hardware initiated, int instructions, and instruction exceptions. hardware initiated interrupts occur in response to an external input and are classified as non-maskable or maska- ble. 14
m80c186 270500 7 note: * supported by using a numeric data coprocessor with the m80c186. figure 7. m80c186 supported data types programs may cause an interrupt with an int in- struction. instruction exceptions occur when an un- usual condition, which prevents further instruction processing, is detected while attempting to execute an instruction. if the exception was caused by exe- cuting an esc instruction with the esc trap bit set in the relocation register, the return instruction will point to the esc instruction, or to the segment over- ride prefix immediately preceding the esc instruc- tion if the prefix was present. in all other cases, the return address from an exception will point at the instruction immediately following the instruction causing the exception. a table containing up to 256 pointers defines the proper interrupt service routine for each interrupt. in- terrupts 0 31, some of which are used for instruc- tion exceptions, are reserved. table 4 shows the m80c186 predefined types and default priority lev- els. for each interrupt, an 8-bit vector must be sup- plied to the m80c186 which identifies the appropri- ate table entry. exceptions supply the interrupt vector internally. in addition, internal peripherals and noncascaded external interrupts will generate their own vectors through the internal interrupt controller. int instructions contain or imply the vector and al- low access to all 256 interrupts. maskable hardware initiated interrupts supply the 8-bit vector to the cpu during an interrupt acknowledge bus sequence. non-maskable hardware interrupts use a predefined internally supplied vector. interrupt sources the m80c186 can service interrupts generated by software or hardware. the software interrupts are generated by specific instructions (int, esc, unused op, etc.) or the results of conditions specified by instructions (array bounds check, int0, div, idiv, etc.). all interrupt sources are serviced by an indirect call through an element of a vector table. this vector table is indexed by using the interrupt vector type (table 4), multiplied by four. all hardware-generated interrupts are sampled at the end of each instruc- tion. thus, the software interrupts will begin service first. once the service routine is entered and inter- rupts are enabled, any hardware source of sufficient priority can interrupt the service routine in progress. the software generated m80c186 interrupts are de- scribed below. divide error exception (type 0) generated when a div or idiv instruction quotient cannot be expressed in the number of bits in the destination. single-step interrupt (type 1) generated after most instructions if the tf flag is set. interrupts will not be generated after prefix in- structions (e.g., rep), instructions which modify seg- ment registers (e.g., pop ds), or the wait instruc- tion. non-maskable interruptenmi (type 2) an external interrupt source which cannot be masked. 15
m80c186 table 4. m80c186 interrupt vectors interrupt vector default related name type priority (4) instructions divide error 0 1 (1) div, idiv exception single step 1 12 (2) all interrupt nmi 2 1 all breakpoint 3 1 (1) int interrupt int0 detected 4 1 (1) int0 overflow exception array bounds 5 1 (1) bound exception unused-opcode 6 1 (1) undefined exception opcodes esc opcode 7 1 (1), (5) esc opcodes exception timer 0 interrupt 8 2a (3) timer 1 interrupt 18 2b (3) timer 2 interrupt 19 2c (3) reserved 9 3 dma 0 interrupt 10 4 dma 1 interrupt 11 5 int0 interrupt 12 6 int1 interrupt 13 7 int2 interrupt 14 8 int3 interrupt 15 9 notes: 1. these are generated as the result of an instruction exe- cution. 2. this is handled as in the m8086. 3. all three timers constitute one source of request to the interrupt controller. the timer interrupts all have the same default priority level with respect to all other interrupt sources. however, they have a defined priority ordering amongst themselves. (priority 2a is higher priority than 2b.) each timer interrupt has a separate vector type number. 4. default priorities for the interrupt sources are used only if the user does not program each source into a unique prior- ity level. 5. an escape opcode will cause a trap if the m80c186 is in compatible mode or if the processor is in enhanced mode with the proper bit set in the peripheral control block relo- cation register. breakpoint interrupt (type 3) a one-byte version of the int instruction. it uses 12 as an index into the service routine address table (because it is a type 3 interrupt). int0 detected overflow exception (type4) generated during an int0 instruction if the 0f bit is set. array bounds exception (type 5) generated during a bound instruction if the array index is outside the array bounds. the array bounds are located in memory at a location indicated by one of the instruction operands. the other operand indi- cates the value of the index to be checked. unused opcode exception (type 6) generated if execution is attempted on undefined opcodes. escape opcode exception (type 7) generated if execution is attempted of esc opcodes (d8h dfh). in compatible mode operation, esc opcodes will always generate this exception. in en- hanced mode operation, the exception will be gener- ated only if a bit in the relocation register is set. the return address of this exception will point to the esc instruction causing the exception. if a segment over- ride prefix preceded the esc instruction, the return address will point to the segment override prefix. hardware-generated interrupts are divided into two groups: maskable interrupts and non-maskable in- terrupts. the m80c186 provides maskable hardware interrupt request pins int0 int3. in addition, mask- able interrupts may be generated by the m80c186 integrated dma controller and the integrated timer unit. the vector types for these interrupts is shown in table 4. software enables these inputs by setting the interrupt flag bit (if) in the status word. the in- terrupt controller is discussed in the peripheral sec- tion of this data sheet. further maskable interrupts are disabled while serv- icing an interrupt because the if bit is reset as part of the response to an interrupt or exception. the saved status word will reflect the enable status of the processor prior to the interrupt. the interrupt flag will remain zero unless specifically set. the interrupt return instruction restores the status word, thereby restoring the original status of if bit. if the interrupt return re-enables interrupts, and another interrupt is pending, the m80c186 will immediately service the highest-priority interrupt pending, i.e., no instructions of the main line program will be executed. non-maskable interrupt request (nmi) a non-maskable interrupt (nmi) is also provided. this interrupt is serviced regardless of the state of the if bit. a typical use of nmi would be to activate a power failure routine. the activation of this input causes an interrupt with an internally supplied vector value of 2. no external interrupt acknowledge se- quence is performed. the if bit is cleared at the beginning of an nmi interrupt to prevent maskable interrupts from being serviced. 16
m80c186 single-step interrupt the m80c186 has an internal interrupt that allows programs to execute one instruction at a time. it is called the single-step interrupt and is controlled by the single-step flag bit (tf) in the status word. once this bit is set, an internal single-step interrupt will occur after the next instruction has been executed. the interrupt clears the tf bit and uses an internally supplied vector of 1. the iret instruction is used to set the tf bit and transfer control to the next instruc- tion to be single-stepped. initialization and processor reset processor initialization or startup is accomplished by driving the res input pin low. res forces the m80c186 to terminate all execution and local bus activity. no instruction or bus activity will occur as long as res is active. after res becomes inactive and an internal processing interval elapses, the m80c186 begins execution with the instruction at physical location ffff0(h). res also sets some registers to predefined values as shown in table 5. table 5. m80c186 initial register state after reset status word f002(h) instruction pointer 0000(h) code segment ffff(h) data segment 0000(h) extra segment 0000(h) stack segment 0000(h) relocation register 20ff(h) umcs fffb(h) m80c186 clock generator the m80c186 provides an on-chip clock generator for both internal and external clock generation. the clock generator features a crystal oscillator, a divide- by-two counter, synchronous and asynchronous ready inputs, and reset circuitry. oscillator the m80c186 oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal, depending upon the frequency range of the application as shown in fig- ure 8a. this is used as the time base for the m80c186. the crystal frequency chosen should be twice the required processor frequency. use of an lc or rc circuit is not recommended. the oscillator output is not directly available external to the m80c186. the two recommended crys- tal configurations are shown in figures 8b and 8c. when used in third-overtone mode the tank circuit shown in figure 8b is recommended for stable oper- ation. the sum of the stray capacitances and load- ing capacitors should equal the values shown. it is advisable to limit stray capacitance between the x1 and x2 pins to less than 10 pf. while a fundamen- tal-mode circuit will require approximately 1 ms for start-up, the third-overtone arrangement may require 1 ms to 3 ms to stabilize. alternately the oscillator pins may be driven from an external source as shown in figure 8d or figure 8e. the configuration shown in figure 8f is not recom- mended. the following parameters may be used for choosing a crystal: temperature range: b 55 cto a 125 c esr (equivalent series resistance): 40 x max c 0 (shunt capacitance of crystal): 7.0 pf max c 1 (load capacitance): 20 pf g 2pf drive level: 1 mw max clock generator the m80c186 clock generator provides the 50% duty cycle processor clock for the m80c186. it does this by dividing the oscillator output by 2 forming the symmetrical clock. if an external oscillator is used, the state of the clock generator will change on the falling edge of the oscillator signal. the clkout pin provides the processor clock signal for use outside the m80c186. this may be used to drive other sys- tem components. all timings are referenced to the output clock. ready synchronization the m80c186 provides both synchronous and asyn- chronous ready inputs. asynchronous ready syn- chronization is accomplished by circuitry which sam- ples ardy in the middle of t 2 ,t 3 and again in the middle of each t w until ardy is sampled high. one-half clkout cycle of resolution time is used. full synchronization is performed only on the rising edge of ardy, i.e., the falling edge of ardy must be synchronized to the clkout signal if it will occur during t 2 ,t 3 ,ort w . high-to-low transitions of ardy must be performed synchronously to the cpu clock. a second ready input (srdy) is provided to inter- face with externally synchronized ready signals. this input is sampled at the end of t 2 ,t 3 and again at the end of each t w until it is sampled high. by using this input rather than the asynchronous ready input, the half-clock cycle resolution time penalty is eliminated. 17
m80c186 270500 8 (8a) 270500 25 (8b) (8c) 270500 24 note 1: xtal frequency l1 value 20 mhz 12.0 m h g 20% 25 mhz 8.2 m h g 20% (8d) 270500 26 (8e) 270500 27 (8f) 270500 28 figure 8. m80c186 oscillator configurations 18
m80c186 this input must satisfy set-up and hold times to guar- antee proper operation of the circuit. in addition, the m80c186, as part of the integrated chip-select logic, has the capability to program wait states for memory and peripheral blocks. this is dis- cussed in the chip select/ready logic description. reset logic the m80c186 provides both a res input pin and a synchronized reset pin for use with other system components. the res input pin on the m80c186 is provided with hysteresis in order to facilitate power- on reset generation via an rc network. reset is guaranteed to remain active for at least five clocks given a res input of at least six clocks. reset may be delayed up to two and one-half clocks behind res . multiple m80c186 processors may be synchronized through the res input pin, since this input resets both the processor and divide-by-two internal coun- ter in the clock generator. in order to insure that the divide-by-two counters all begin counting at the same time, the active going edge of res must satis- fy a 25 ns setup time before the falling edge of the m80c186 clock input. in addition, in order to insure that all cpus begin executing in the same clock cy- cle, the reset must satisfy a 15 ns setup time before the rising edge of the clkout signal of all the proc- essors. local bus controller the m80c186 provides a local bus controller to gen- erate the local bus control signals. in addition, it em- ploys a hold/hlda protocol for relinquishing the local bus to other bus masters. it also provides con- trol lines that can be used to enable external buffers and to direct the flow of data on and off the local bus. memory/peripheral control the m80c186 provides ale, rd , and wr bus con- trol signals. the rd and wr signals are used to strobe data from memory to the m80c186 or to strobe data from the m80c186 to memory. the ale line provides a strobe to address latches for the mul- tiplexed address/data bus. the m80c186 local bus controller does not provide a memory/i/o signal. if this is required, the user will have to use the s2 sig- nal (which will require external latching), make the memory and i/o spaces nonoverlapping, or use only the integrated chip-select circuitry. transceiver control the m80c186 generates two control signals to be connected to external transceiver chips. this capa- bility allows the addition of transceivers for extra buffering without adding external logic. these con- trol lines, dt/r and den , are generated to control the flow of data through the transceivers. the opera- tion of these signals is shown in table 6. table 6. transceiver control signals description pin name function den (data enable) enables the output drivers of the transceivers. it is active low during memory, i/o, or inta cycles. dt/r (data transmit/ determines the direction receive) of travel through the transceivers. a high level directs data away from the processor during write operations, while a low level directs data toward the processor during a read operation. local bus arbitration the m80c186 uses a hold/hlda system of local bus exchange. this provides an asynchronous bus exchange mechanism. this means multiple masters utilizing the same bus can operate at separate clock frequencies. the m80c186 provides a single hold/ hlda pair through which all other bus masters may gain control of the local bus. this requires external circuitry to arbitrate which external device will gain control of the bus from the m80c186 when there is more than one alternate local bus master. when the m80c186 relinquishes control of the local bus, it floats den ,rd ,wr ,s0 s2 , lock , ad0 ad15, a16 a19, bhe , and dt/r to allow another master to drive these lines directly. the m80c186 hold latency time, i.e., the time be- tween hold request and hold acknowledge, is a function of the activity occurring in the processor when the hold request is received. a hold re- quest is the highest-priority activity request which the processor may receive: higher than instruction fetching or internal dma cycles. however, if a dma cycle is in progress, the m80c186 will complete the transfer before relinquishing the bus. this implies that if a hold request is received just as a dma transfer begins, the hold latency time can be as great as 4 bus cycles. this will occur if a dma word transfer operation is taking place from an odd ad- 19
m80c186 dress to an odd address. this is a total of 16 clocks or more, if wait states are required. in addition, if locked transfers are performed, the hold latency time will be increased by the length of the locked transfer. local bus controller and reset upon receipt of a reset pulse from the res input, the local bus controller will perform the following ac- tion: # drive den ,rd , and wr high for one clock cy- cle, then float. note: rd is also provided with an internal pull-up device to prevent the processor from inadvertently enter- ing queue status mode during reset. # drive s0 s2 to the passive state (all high) and then float. # drive lock high and then float. # float ad0 15, a16 19, bhe , dt/r . # drive ale low (ale is never floated). # drive hlda low. internal peripheral interface all the m80c186 integrated peripherals are con- trolled via 16-bit registers contained within an inter- nal 256-byte control block. this control block may be mapped into either memory or i/o space. internal logic will recognize the address and respond to the bus cycle. during bus cycles to internal registers, the bus controller will signal the operation externally (i.e., the rd ,wr , status, address, data, etc., lines will be driven as in a normal bus cycle), but d 150 , srdy, and ardy will be ignored. the base address of the control block must be on an even 256-byte boundary (i.e., the lower 8 bits of the base address are all zeros). all of the defined registers within this control block may be read or written by the m80c186 cpu at any time. the location of any reg- ister contained within the 256-byte control block is determined by the current base address of the con- trol block. the control block base address is programmed via a 16-bit relocation register contained within the control block at offset feh from the base address of the control block (see figure 9). it provides the upper 12 bits of the base address of the control block. the control block is effectively an internal chip select range and must abide by all the rules concerning chip selects (the chip select circuitry is discussed later in this data sheet). any access to the 256 bytes of the control block activates an internal chip select. other chip selects may overlap the control block only if they are programmed to zero wait states and ignore external ready. in addition, bit 12 of this regis- ter determines whether the control block will be mapped into i/o or memory space. if this bit is 1, the control block will be located in memory space, whereas if the bit is 0, the control block will be locat- ed in i/o space. if the control register block is mapped into i/o space, the upper 4 bits of the base address must be programmed as 0 (since i/o ad- dresses are only 16 bits wide). in addition to providing relocation information for the control block, the relocation register contains bits which place the interrupt controller into slave mode, and cause the cpu to interrupt upon encountering esc instructions. at reset, the relocation register is set to 20ffh. this causes the control block to start at ff00h in i/o space. an offset map of the 256-byte control register block is shown in figure 10. the integrated m80c186 peripherals operate semi- autonomously from the cpu. access to them for the most part is via software read/write of the control block. most of these registers can be both read and written. a few dedicated lines, such as interrupts and dma request provide real-time communication be- tween the cpu and peripherals as in a more con- ventional system utilizing discrete peripheral blocks. the overall interaction and function of the peripheral blocks has not substantially changed. chip-select/ready generation logic the m80c186 contains logic which provides programmable chip-select generation for both memories and peripherals. in addition, it can be pro- grammed to provide ready (or wait state) genera- tion. it can also povide latched address bits a1 and a2. the chip-select lines are active for all memory and i/o cycles in their programmed areas, whether they be generated by the cpu or by the integrated dma unit. memory chip selects the m80c186 provides 6 memory chip select out- puts for 3 address areas; upper memory, lower memory, and midrange memory. one each is provid- ed for upper memory and lower memory, while four are provided for midrange memory. the range for each chip select is user-programma- ble and can be set to 2k, 4k, 8k, 16k, 32k, 64k, 128k (plus 1k and 256k for upper and lower chip selects). in addition, the beginning or base address 20
m80c186 15 14 131211109876543210 offset: feh et slave/master x m/io relocation address bits r19 r8 et e esc trap / no esc trap (1/0) m/io e register block located in memory / i/o space (1/0) slave/master e configures interrupt controller for slave/master mode (1/0) figure 9. relocation register offset relocation register feh dma descriptors channel 1 dah d0h dma descriptors channel 0 cah c0h chip-select control registers a8h a0h time 2 control registers 66h 60h time 1 control registers 5eh 58h time 0 control registers 56h 50h interrupt controller registers 3eh 20h figure 10. internal register map of the midrange memory chip select may also be selected. only one chip select may be programmed to be active for any memory location at a time. m80c186 memory is arranged in words but chip se- lects are sized in bytes. if sixteen 64k x 1 memories are used then the memory block size will be 128k, not 64k. upper memory cs the m80c186 provides a chip select, called ucs , for the top of memory. the top of memory is usually used as the system memory because after reset the m80c186 begins executing at memory location ffff0h. the upper limit of memory defined by this chip select is always fffffh, while the lower limit is program- mable. by programming the lower limit, the size of the select block is also defined. table 7 shows the relationship between the base address selected and the size of the memory block obtained. table 7. umcs programming values starting memory umcs value address block (assuming (base size r0 e r1 e r2 e 0) address) ffc00 1k fff8h ff800 2k ffb8h ff000 4k ff38h fe000 8k fe38h fc000 16k fc38h f8000 32k f838h f0000 64k f038h e0000 128k e038h c0000 256k c038h the lower limit of this memory block is defined in the umcs register (see figure 11). this register is at offset a0h in the internal control block. the legal values for bits 6 13 and the resulting starting ad- dress and memory block sizes are given in table 7. any combination of bits 6 13 not shown in table 7 will result in undefined operation. after reset, the umcs register is programmed for a 1k area. it must be reprogrammed if a larger upper memory area is desired. any internally generated 20-bit address whose up- per 16 bits are greater than or equal to umcs (with bits 0 5 ``0'') will cause ucs to be activated. umcs bits r2 r0 are used to specify ready mode for the area of memory defined by this chip-select register, as explained below. lower memory cs the m80c186 provides a chip select for low memory called lcs . the bottom of memory contains the in- terrupt vector table, starting at location 00000h. 21
m80c186 the lower limit of memory defined by this chip select is always 0h, while the upper limit is programmable. by programming the upper limit, the size of the memory block is also defined. table 8 shows the relationship between the upper address selected and the size of the memory block obtained. table 8. lmcs programming values upper memory lmcs value address block (assuming size r0 e r1 e r2 e 0) 003ffh 1k 0038h 007ffh 2k 0078h 00fffh 4k 00f8h 01fffh 8k 01f8h 03fffh 16k 03f8h 07fffh 32k 07f8h 0ffffh 64k 0ff8h 1ffffh 128k 1ff8h 3ffffh 256k 3ff8h the upper limit of this memory block is defined in the lmcs register (see figure 12). this register is at offset a2h in the internal control block. the legal values for bits 6 15 and the resulting upper address and memory block sizes are given in table 8. any combination of bits 6 15 not shown in table 8 will result in undefined operation. after reset, the lmcs register value is undefined. however, the lcs chip- select line will not become active until the lmcs register is accessed. any internally generated 20-bit address whose up- per 16 bits are less than or equal to lmcs (with bits 0 5 ``1'') will cause lcs to be active. lmcs register bits r2 r0 are used to specify the ready mode for the area of memory defined by this chip-select regis- ter. mid-range memory cs the m80c186 provides four mcs lines which are active within a user-locatable memory block. this block can be located within the m80c186 1m byte memory address space exclusive of the areas de- fined by ucs and lcs . both the base ad- dress and size of this memory block are programma- ble. the size of the memory block defined by the mid- range select lines, as shown in table 9, is deter- mined by bits 8 14 of the mpcs register (see figure 13). this register is at location a8h in the internal control block. one and only one of bits 8 14 must be set at a time. unpredictable operation of the mcs lines will otherwise occur. each of the four chip-se- lect lines is active for one of the four equal contigu- ous divisions of the mid-range block. thus, if the to- tal block size is 32k, each chip select is active for 8k of memory with mcs0 being active for the first range and mcs3 being active for the last range. the ex and ms in mpcs relate to peripheral func- tionally as described in a later section. table 9. mpcs programming values total block individual mpcs bits size select size 14 8 8k 2k 0000001b 16k 4k 0000010b 32k 8k 0000100b 64k 16k 0001000b 128k 32k 0010000b 256k 64k 0100000b 512k 128k 1000000b the base address of the mid-range memory block is defined by bits 15 9 of the mmcs register (see fig- ure 14). this register is at offset a6h in the internal control block. these bits correspond to bits a19 a13 of the 20-bit memory address. bits a12 a0 of the base address are always 0. the base address may be set at any integer multiple of the size of the total memory block selected. for exam- ple, if the mid-range block size is 32k (or the size of the block for which each mcs line is active is 8k), the block could be located at 10000h or 18000h, but not at 14000h, since the first few integer multi- ples of a 32k memory block are 0h, 8000h, 10000h, 18000h, etc. after reset, the contents of both of these registers is undefined. however, none of the mcs lines will be active until both the mmcs and mpcs registers are accessed. 1514131211109876543210 offset: a0h 1 1 uuuuuuuu1 1 1r2r1r0 a19 a11 figure 11. umcs register 1514131211109876543210 offset: a2h 0 0 uuuuuuuu1 1 1r2r1r0 a19 a11 figure 12. lmcs register 22
m80c186 1514131211109876543210 offset: a8h 1 m6 m5 m4 m3 m2 m1 m0 ex ms 1 1 1 r2 r1 r0 figure 13. mpcs register 15 9 3 0 offset: a6h uuuuuuu 111111r2r1r0 a19 a13 figure 14. mmcs register mmcs bits r2 r0 specify ready mode of opera- tion for all mid-range chip selects. all devices in mid- range memory must use the same number of wait states. the 512k block size for the mid-range memory chip selects is a special case. when using 512k, the base address would have to be at either locations 00000h or 80000h. if it were to be programmed at 00000h when the lcs line was programmed, there would be an internal conflict between the lcs ready generation logic and the mcs ready generation log- ic. likewise, if the base address were programmed at 80000h, there would be a conflict with the ucs ready generation logic. since the lcs chip-select line does not become active until programmed, while the ucs line is active at reset, the memory base can be set only at 00000h. if this base address is select- ed, however, the lcs range must not be pro- grammed. peripheral chip selects the m80c186 can generate chip selects for up to seven peripheral devices. these chip selects are ac- tive for seven contiguous blocks of 128 bytes above a programmable base address. this base address may be located in either memory or i/o space. seven cs lines called pcs0 6 are generated by the m80c186. the base address is user-programmable; however it can only be a multiple of 1k bytes, i.e., the least significant 10 bits of the starting address are always 0. pcs5 and pcs6 can also be programmed to provide latched address bits a1, a2. if so programmed, they cannot be used as peripheral selects. these outputs can be connected directly to the a0, a1 pins used for selecting internal registers of 8-bit peripheral chips. this scheme simplifies the hardware interface because the 8-bit registers of peripherals are simply treated as 16-bit registers located on even bounda- ries in i/o space or memory space where only the lower 8-bits of the register are significant: the upper 8-bits are ``don't cares.'' the starting address of the peripheral chip-select block is defined by the pacs register (see figure 15). this register is located at offset a4h in the inter- nal control block. bits 15 6 of this register corre- spond to bits 19 10 of the 20-bit programmable base address (pba) of the peripheral chip-select block. bits 9 0 of the pba of the peripheral chip-se- lect block are all zeros. if the chip-select block is located in i/o space, bits 12 15 must be pro- grammed zero, since the i/o address is only 16 bits wide. table 10 shows the address range of each peripheral chip select with respect to the pba con- tained in pacs register. 15 6 5 3 0 offset: a4h uuuuuuuuuu1 1 1r2r1r0 a19 a10 figure 15. pacs register 23
m80c186 the user should program bits 15 6 to correspond to the desired peripheral base location. pacs bits 0 2 are used to specify ready mode for pcs0 pcs3 . table 10. pcs address ranges pcs line active between locations pcs0 pba epba a 127 pcs1 pba a 128epba a 255 pcs2 pba a 256epba a 383 pcs3 pba a 384epba a 511 pcs4 pba a 512epba a 639 pcs5 pba a 640epba a 767 pcs6 pba a 768epba a 895 the mode of operation of the peripheral chip selects is defined by the mpcs register (which is also used to set the size of the mid-range memory chip-select block, see figure 13). this register is located at off- set a8h in the internal control block. bit 7 is used to select the function of pcs5 and pcs6 , while bit 6 is used to select whether the peripheral chip selects are mapped into memory or i/o space. table 11 describes the programming of these bits. after reset, the contents of both the mpcs and the pacs regis- ters are undefined, however none of the pcs lines will be active until both of the mpcs and pacs reg- isters are accessed. table 11. ms, ex programming values bit description ms 1 e peripherals mapped into memory space. 0 e peripherals mapped into i/o space. ex 0 e 5 pcs lines. a1, a2 provided. 1 e 7 pcs lines. a1, a2 are not provided. mpcs bits 0 2 are used to specify ready mode for pcs4 pcs6 as outlined below. ready generation logic the m80c186 can generate a ``ready'' signal in- ternally for each of the memory or peripheral cs lines. the number of wait states to be inserted for each peripheral or memory is programmable to pro- vide 0 3 wait states for all accesses to the area for which the chip select is active. in addition, the m80c186 may be programmed to either ignore ex- ternal ready for each chip-select range individually or to factor external ready with the integrated ready generator. ready control consists of 3 bits for each cs line or group of lines generated by the m80c186. the inter- pretation of the ready bits is shown in table 12. table 12. ready bits programming r2 r1 r0 number of wait states generated 0 0 0 0 wait states, external rdy also used. 0 0 1 1 wait state inserted, external rdy also used. 0 1 0 2 wait states inserted, external rdy also used. 0 1 1 3 wait states inserted, external rdy also used. 1 0 0 0 wait states, external rdy ignored. 1 0 1 1 wait state inserted, external rdy ignored. 1 1 0 2 wait states inserted, external rdy ignored. 1 1 1 3 wait states inserted, external rdy ignored. the internal ready generator operates in parallel with external ready, not in series if the external ready is used (r2 e 0). this means, for example, if the internal generator is set to insert two wait states, but activity on the external ready lines will insert four wait states, the processor will only insert four wait states, not six. this is because the two wait states generated by the internal generator over- lapped the first two wait states generated by the ex- ternal ready signal. note that the external ardy and srdy lines are always ignored during cycles ac- cessing internal peripherals. r2 r0 of each control word specifies the ready mode for the corresponding block, with the excep- tion of the peripheral chip selects: r2 r0 of pacs set the pcs0 3 ready mode, r2 r0 of mpcs set the pcs4 6 ready mode. chip select/ready logic and reset upon reset, the chip-select/ready logic will per- form the following actions: # all chip-select outputs will be driven high. # upon leaving reset, the ucs line will be pro- grammed to provide chip selects to a 1k block with the accompanying ready control bits set at 011 to allow the maximum number of internal wait states in conjunction with external ready consid- eration (i.e., umcs resets to fffbh). # no other chip select or ready control registers have any predefined values after reset. they will not become active until the cpu accesses their control registers. both the pacs and mpcs registers must be accessed before the pcs lines will become active. 24
m80c186 dma channels the m80c186 dma controller provides two indepen- dent high-speed dma channels. data transfers can occur between memory and i/o spaces (e.g., mem- ory to i/o) or within the same space (e.g., memory to memory or i/o to i/o). data can be transferred either in bytes (8 bits) or in words (16 bits) to or from even or odd addresses. each dma channel main- tains both a 20-bit source and destination pointer which can be optionally incremented or decrement- ed after each data transfer (by one or two depending on byte or word transfers). each data transfer con- sumes 2 bus cycles (a minimum of 8 clocks), one cycle to fetch data and the other to store data. dma operation each channel has six registers in the control block which define each channel's specific operation. the control registers consist of a 20-bit source pointer (2 words), a 20-bit destination pointer (2 words), a 16- bit transfer counter, and a 16-bit control word. the format of the dma control blocks is shown in table 13. the transfer count register (tc) specifies the number of dma transfers to be performed. up to 64k byte or word transfers can be performed with automatic termination. the control word defines the channel's operation (see figure 17). all registers may be modified or altered during any dma activity. any changes made to these registers will be reflect- ed immediately in dma operation. table 13. dma control block format register name register address ch. 0 ch. 1 control word cah dah transfer count c8h d8h destination pointer (upper 4 c6h d6h bits) destination pointer c4h d4h source pointer (upper 4 bits) c2h d2h source pointer c0h d0h 270500 9 figure 16. dma unit block diagram 25
m80c186 1514131211109876543 2 10 t d m/ destination m/ source tc int syn p r x chg/ st/ b / io dec inc io dec inc q nochg stop w x e don't care. figure 17. dma control register dma channel control word register each dma channel control word determines the mode of operation for the particular m80c186 dma channel. this register specifies: # the mode of synchronization; # whether bytes or words will be transferred; # whether interrupts will be generated after the last transfer; # whether dma activity will cease after a pro- grammed number of dma cycles; # the relative priority of the dma channel with re- spect to the other dma channel; # whether the source pointer will be incremented, decremented, or maintained constant after each transfer; # whether the source pointer addresses memory or i/o space; # whether the destination pointer will be increment- ed, decremented, or maintained constant after each transfer; and # whether the destination pointer will address memory or i/o space. the dma channel control registers may be changed while the channel is operating. however, any chang- es made during operation will affect the current dma transfer. dma control word bit descriptions b /w: byte/word (0/1) transfers. st/stop : start/stop (1/0) channel. chg/nochg : change/do not change (1/0) st/stop bit. if this bit is set when writing to the control word, the st/stop bit will be programmed by the write to the control word. if this bit is cleared when writing the control word, the st/stop bit will not be altered. this bit is not stored; it will always be a 0 on read. int: enable interrupts to cpu on transfer count termination. tc: if set, dma will terminate when the contents of the transfer count register reach zero. the st/stop bit will also be reset at this point if tc is set. if this bit is cleared, the dma unit will decrement the trans- fer count register for each dma cycle, but the dma transfer will not stop when the contents of the tc register reach zero. syn 00 no synchronization. note: when unsynchronized transfers are specified, the tc bit will be ig- nored and the st bit will be cleared upon the transfer count reaching zero, stopping the chan- nel. (2 bits) 01 source synchronization. 10 destination synchronization. 11 unused. source:inc increment source pointer by 1 or 2 (depends on b /w) after each transfer. m/io source pointer is in m/io space (1/0). dec decrement source pointer by 1 or 2 (depends on b /w) after each transfer. dest: inc increment destination pointer by 1 or 2 (b /w) after each transfer. m/io destination pointer is in m/io space (1/0). dec decrement destination pointer by 1 or 2 (depending on b /w) after each transfer. p channel priorityerelative to other channel. 0 low priority. 1 high priority. channels will alternate cycles if both set at same priority level. tdrq 0: disable dma requests from tim- er 2. 1: enable dma requests from tim- er 2. bit 3 bit 3 is not used. 26
m80c186 if both inc and dec are specified for the same pointer, the pointer will remain constant after each cycle. dma destination and source pointer registers each dma channel maintains a 20-bit source and a 20-bit destination pointer. each of these pointers takes up two full 16-bit registers in the peripheral control block. the lower four bits of the upper regis- ter contain the upper four bits of the 20-bit physical address (see figure 18). these pointers may be indi- vidually incremented or decremented after each transfer. if word transfers are performed the pointer is incremented or decremented by two. each pointer may point into either memory or i/o space. since the dma channels can perform transfers to or from odd addresses, there is no restriction on values for the pointer registers. higher transfer rates can be obtained if all word transfers are performed to even addresses, since this will allow data to be accessed in a single memory access. dma transfer count register each dma channel maintains a 16-bit transfer count register (tc). this register is decremented after ev- ery dma cycle, regardless of the state of the tc bit in the dma control register. if the tc bit in the dma control word is set or if unsynchronized transfers are programmed, however, dma activity will terminate when the transfer count register reaches zero. dma requests data transfers may be either source or destination synchronized, that is either the source of the data or the destination of the data may request the data transfer. in addition, dma transfers may be unsyn- chronized; that is, the transfer will take place contin- ually until the correct number of transfers has oc- curred. when source or unsynchronized transfers are performed, the dma channel may begin another transfer immediately after the end of a previous dma transfer. this allows a complete transfer to take place every 2 bus cycles or eight clock cycles (assuming no wait states). no prefetching occurs when destination synchronization is performed, how- ever. data will not be fetched from the source ad- dress until the destination device signals that it is ready to receive it. when destination synchronized transfers are requested, the dma controller will re- linquish control of the bus after every transfer. if no other bus activity is initiated, another dma cycle will begin after two processor clocks. this is done to allow the destination device time to remove its re- quest if another transfer is not desired. since the dma controller will relinquish the bus, the cpu can initiate a bus cycle. as a result, a complete bus cycle will often be inserted between destination synchro- nized transfers. these lead to the maximum dma transfer rates shown in table 14. table 14. maximum dma transfer rates type of synchronization cpu running cpu halted selected unsynchronized 2.5mbytes/sec 2.5mbytes/sec source synch 2.5mbytes/sec 2.5mbytes/sec destination synch 1.7mbytes/sec 2.0mbytes/sec higher register xxx xxx xxx a19a16 address lower register a15a12 a11a8 a7a4 a3a0 address 15 0 xxx e don't care figure 18. dma memory pointer register format 27
m80c186 dma acknowledge no explicit dma acknowledge pulse is provided. since both source and destination pointers are maintained, a read from a requesting source, or a write to a requesting destination, should be used as the dma acknowledge signal. since the chip-select lines can be programmed to be active for a given block of memory or i/o space, and the dma point- ers can be programmed to point to the same given block, a chip-select line could be used to indicate a dma acknowledge. dma priority the dma channels may be programmed such that one channel is always given priority over the other, or they may be programmed such as to alternate cycles when both have dma requests pending. dma cycles always have priority over internal cpu cycles except between locked memory accesses or word accesses to odd memory locations; however, an ex- ternal bus hold takes priority over an internal dma cycle. because an interrupt request cannot suspend a dma operation and the cpu cannot access mem- ory during a dma cycle, interrupt latency time will suffer during sequences of continuous dma cycles. an nmi request, however, will cause all internal dma activity to halt. this allows the cpu to quickly respond to the nmi request. dma programming dma cycles will occur whenever the st/stop bit of the control register is set. if synchronized transfers are programmed, a drq must also have been gen- erated. therefore the source and destination trans- fer pointers, and the transfer count register (if used) must be programmed before this bit is set. each dma register may be modified while the chan- nel is operating. if the chg/nochg bit is cleared when the control register is written, the st/stop bit of the control register will not be modified by the write. if multiple channel registers are modified, it is recommended that a locked string transfer be used to prevent a dma transfer from occurring be- tween updates to the channel registers. dma channels and reset upon reset, the dma channels will perform the following actions: # the start/stop bit for each channel will be reset to stop. # any transfer in progress is aborted. timers the m80c186 provides three internal 16-bit pro- grammable timers (see figure 19). two of these are highly flexible and are connected to four external pins (2 per timer). they can be used to count exter- nal events, time external events, generate nonrepet- itive waveforms, etc. the third timer is not connect- ed to any external pins, and is useful for real-time coding and time delay applications. in addition, this third timer can be used as a prescaler to the other two, or as a dma request source. 270500 10 figure 19. timer block diagram 28
m80c186 timer operation the timers are controlled by 11 16-bit registers in the internal peripheral control block. the configura- tion of these registers is shown in table 15. the count register contains the current value of the tim- er. it can be read or written at any time independent of whether the timer is running or not. the value of this register will be incremented for each timer event. each of the timers is equipped with a max count register, which defines the maximum count the timer will reach. after reaching the max count register value, the timer count value will reset to zero during that same clock, i.e., the maximum count val- ue is never stored in the count register itself. timers 0 and 1 are, in addition, equipped with a second max count register, which enables the timers to alternate their count between two different max count values programmed by the user. if a single max count register is used, the timer output pin will switch low for a single clock, 1 clock after the maximum count value has been reached. in the dual max count register mode, the output pin will indi- cate which max count register is currently in use, thus allowing nearly complete freedom in selecting waveform duty cycles. for the timers with two max count registers, the riu bit in the control register determines which is used for the comparison. each timer gets serviced every fourth cpu-clock cy- cle, and thus can operate at speeds up to one-quar- ter the internal clock frequency (one-eighth the crys- tal rate). external clocking of the timers may be done at up to a rate of one-quarter of the internal cpu- clock rate. due to internal synchronization and pipe- lining of the timer circuitry, a timer output may take up to 6 clocks to respond to any individual clock or gate input. since the count registers and the maximum count registers are all 16 bits wide, 16 bits of resolution are provided. any read or write access to the timers will add one wait state to the minimum four-clock bus cycle, however. this is needed to synchronize and coordinate the internal data flows between the inter- nal timers and the internal bus. the timers have several programmable options. # all three timers can be set to halt or continue on a terminal count. # timers 0 and 1 can select between internal and external clocks, alternate between max count registers and be set to retrigger on external events. # the timers may be programmed to cause an in- terrupt on terminal count. these options are selectable via the timer mode/ control word. timer mode/control register the mode/control register (see figure 20) allows the user to program the specific mode of operation or check the current programmed status for any of the three integrated timers. table 15. timer control block format register name register offset tmr. 0 tmr. 1 tmr. 2 mode/control word 56h 5eh 66h max count b 54h 5ch not present max count a 52h 5ah 62h count register 50h 58h 60h 15 14 13 12 11 5 4 3 2 1 0 en inh int riu 0 . . . mc rtg p ext alt cont figure 20. timer mode/control register 29
m80c186 alt: the alt bit determines which of two max count registers is used for count comparison. if alt e 0, register a for that timer is always used, while if alt e 1, the comparison will alternate between register a and register b when each maximum count is reached. this alternation allows the user to change one max count register while the other is being used, and thus provides a method of generating non-repetitive waveforms. square waves and pulse outputs of any duty cycle are a subset of available signals obtained by not changing the final count reg- isters. the alt bit also determines the function of the timer output pin. if alt is zero, the output pin will go low for one clock, the clock after the maximum count is reached. if alt is one, the output pin will reflect the current max count register being used (0/1 for b/a). cont: setting the cont bit causes the associated timer to run continuously, while resetting it causes the timer to halt upon maximum count. if count e 0 and alt e 1, the timer will count to the max count register a value, reset, count to the register b value, reset, and halt. ext: the external bit selects between internal and exter- nal clocking for the timer. the external signal may be asynchronous with respect to the m80c186 clock. if this bit is set, the timer will count low-to- high transitions on the input pin. if cleared, it will count an internal clock while using the input pin for control. in this mode, the function of the external pin is defined by the rtg bit. the maximum input to output transition latency time may be as much as 6 clocks. however, clock inputs may be pipelined as closely together as every 4 clocks without losing clock pulses. p: the prescaler bit is ignored unless internal clocking has been selected (ext e 0). if the p bit is a zero, the timer will count at one-fourth the internal cpu clock rate. if the p bit is a one, the output of timer 2 will be used as a clock for the timer. note that the user must initialize and start timer 2 to obtain the prescaled clock. rtg: retrigger bit is only active for internal clocking (ext e 0). in this case it determines the control function provided by the input pin. if rtg e 0, the input level gates the internal clock on and off. if the input pin is high, the timer will count; if the input pin is low, the timer will hold its value. as indicated previously, the input signal may be asynchronous with respect to the m80c186 clock. when rtg e 1, the input pin detects low-to-high transitions. the first such transition starts the timer running, clearing the timer value to zero on the first clock, and then incrementing thereafter. further transitions on the input pin will again reset the timer to zero, from which it will start counting up again. if cont e 0, when the timer has reached maximum count, the en bit will be cleared, inhibiting further timer activity. en: the enable bit provides programmer control over the timer's run/halt status. when set, the timer is enabled to increment subject to the input pin con- straints in the internal clock mode (discussed previ- ously). when cleared, the timer will be inhibited from counting. all input pin transistions during the time en is zero will be ignored. if cont is zero, the en bit is automatically cleared upon maximum count. inh : the inhibit bit allows for selective updating of the enable (en) bit. if inh is a one during the write to the mode/control word, then the state of the en bit will be modified by the write. if inh is a zero during the write, the en bit will be unaffected by the operation. this bit is not stored; it will always b ea0ona read. int: when set, the int bit enables interrupts from the timer, which will be generated on every terminal count. if the timer is configured in dual max count register mode, an interrupt will be generated each time the value in max count register a is reached, and each time the value in max count register b is reached. if this enable bit is cleared after the inter- rupt request has been generated, but before a pend- ing interrupt is serviced, the interrupt request will still be in force. (the request is latched in the interrupt controller). mc: the maximum count bit is set whenever the timer reaches its final maximum count value. if the timer is configured in dual max count register mode, this bit will be set each time the value in max count register a is reached, and each time the value in max count register b is reached. this bit is set 30
m80c186 regardless of the timer's interrupt-enable bit. the mc bit gives the user the ability to monitor timer status through software instead of through inter- rupts. programmer intervention is required to clear this bit. riu: the register in use bit indicates which max count register is currently being used for compari- son to the timer count value. a zero value indicates register a. the riu bit cannot be written, i.e., its value is not affected when the control register is writ- ten. it is always cleared when the alt bit is zero. not all mode bits are provided for timer 2. certain bits are hardwired as indicated below: alt e 0, ext e 0, p e 0, rtg e 0, riu e 0 count registers each of the three timers has a 16-bit count register. the current contents of this register may be read or written by the processor at any time. if the register is written into while the timer is counting,the new value will take effect in the current count cycle. max count registers timers 0 and 1 have two max count registers, while timer 2 has a single max count register. these contain the number of events the timer will count. in timers 0 and 1, the max count register used can alternate between the two max count val- ues whenever the current maximum count is reached. the condition which causes a timer to re- set is equivalent between the current count value and the max count being used. this means that if the count is changed to be above the max count value, or if the max count value is changed to be below the current value, the timer will not reset to zero, but rather will count to its maximum value, ``wrap around'' to zero, then count until the max count is reached. timers and reset upon reset, the timers will perform the following actions: # all en (enable) bits are reset preventing timer counting. # all sel (select) bits are reset to zero. this se- lects max count register a, resulting in the timer out pins going high upon reset. interrupt controller the m80c186 can receive interrupts from a number of sources, both internal and external. the internal interrupt controller serves to merge these requests on a priority basis, for individual service by the cpu. internal interrupt sources (timers and dma chan- nels) can be disabled by their own control registers or by mask bits within the interrupt controller. the m80c186 interrupt controller has its own control register that set the mode of operation for the con- troller. the interrupt controller will resolve priority among requests that are pending simultaneously. nesting is provided so interrupt service routines for lower priori- ty interrupts may themselves be interrupted by high- er priority interrupts. a block diagram of the interrupt controller is shown in figure 21. the m80c186 has a special slave mode in which the internal interrupt controller acts as a slave to an ex- ternal master. the controller is programmed into this mode by setting bit 14 in the peripheral control block relocation register. (see slave mode section.) master mode operation interrupt controller external interface for external interrupt sources, five dedicated pins are provided. one of these pins is dedicated to nmi, non-maskable interrupt. this is typically used for power-fail interrupts, etc. the other four pins may function either as four interrupt input lines with inter- nally generated interrupt vectors, as an interrupt line and an interrupt acknowledge line (called the ``cas- cade mode'') along with two other input lines with internally generated interrupt vectors, or as two in- terrupt input lines and two dedicated interrupt ac- knowledge output lines. when the interrupt lines are configured in cascade mode, the m80c186 interrupt controller will not generate internal interrupt vectors. external sources in the cascade mode use external- ly generated interrupt vectors. when an interrupt is acknowledged, two inta cycles are initiated and the vector is read into the m80c186 on the second cy- cle. the capability to interface to external m82c59a programmable interrupt controllers is thus provided when the inputs are configured in cascade mode. 31
m80c186 interrupt controller modes of operation the basic modes of operation of the interrupt con- troller in master mode are similar to the m82c59a. the interrupt controller responds indentically to in- ternal interrupts in all three modes: the difference is only in the interpretation of function of the four exter- nal interrupt pins. the interrupt controller is set into one of these three modes by programming the cor- rect bits in the int0 and int1 control registers. the modes of interrupt controller operation are as fol- lows: fully nested mode when in the fully nested mode four pins are used as direct interrupt requests as in figure 22. the vectors for these four inputs are generated internally. an in- service bit is provided for every interrupt source. if a lower-priority device requests an interrupt while the in service bit (is) is set, no interrupt will be generat- ed by the interrupt controller. in addition, if another interrupt request occurs from the same interrupt source while the in-service bit is set, no interrupt will be generated by the interrupt controller. this allows interrupt service routines to operate with interrupts enabled without being themselves interrupted by lower-priority interrupts. since interrupts are en- abled, higher-priority interrupts will be serviced. when a service routine is completed, the proper is bit must be reset by writing the proper pattern to the eoi register. this is required to allow subsequent interrupts from this interrupt source and to allow servicing of lower-priority interrupts. an eoi com- mand is issued at the end of the service routine just before the issuance of the return from interrupt in- struction. if the fully nested structure has been up- held, the next highest-priority source with its is bit set is then serviced. cascade mode the m80c186 has four interrupt pins and two of them have dual functions. in the fully nested mode the four pins are used as direct interrupt inputs and the corresponding vectors are generated internally. in the cascade mode, the four pins are configured into interrupt input-dedicated acknowledge signal pairs. the interconnection is shown in figure 23. int0 is an interrupt input interfaced to an m82c59a, while int2/inta0 serves as the dedicated interrupt acknowledge signal to that peripheral. the same is true for int1 and int3/inta1 . each pair can selec- tively be placed in the cascade or non-cascade mode by programming the proper value into int0 and int1 control registers. the use of the dedicated acknowledge signals eliminates the need for the use of external logic to generate inta and device select signals. the primary cascade mode allows the capability to serve up to 128 external interrupt sources through the use of external master and slave m82c59as. three levels of priority are created, requiring priority resolution in the m80c186 interrupt controller, the master m82c59as, and the slave m82c59as. if an external interrupt is serviced, one is bit is set at each of these levels. when the interrupt service rou- tine is completed, up to three end-of-interrupt com- mands must be issued by the programmer. 270500 11 figure 21. interrupt controller block diagram 32
m80c186 270500 22 figure 22. fully nested (direct) mode interrupt controller connections special fully nested mode this mode is entered by setting the sfnm bit in int0 or int1 control register. it enables complete nestability with external m82c59a masters. normal- ly, an interrupt request from an interrupt source will not be recognized unless the in-service bit for that source is reset. if more than one interrupt source is connected to an external interrupt controller, all of the interrupts will be funneled through the same m80c186 interrupt request pin. as a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt will not be recognized by the m80c186 controller until the m80c186 in-service bit is reset. in special fully nested mode, the m80c186 interrupt controller will allow interrupts from an exter- nal pin regardless of the state of the in-service bit for an interrupt source in order to allow multiple inter- rupts from a single pin. an in-service bit will continue to be set, however, to inhibit interrupts from other lower-priority m80c186 interrupt sources. special procedures should be followed when reset- ting is bits at the end of interrupt service routines. software polling of the external master's is register is required to determine if there is more than one bit set. if so, the is bit in the m80c186 remains active and the next interrupt service routine is entered. operation in a polled environment the controller may be used in a polled mode if inter- rupts are undesirable. when polling, the processor disables interrupts and then polls the interrupt con- troller whenever it is convenient. polling the interrupt controller is accomplished by reading the poll word (figure 32). bit 15 in the poll word indicates to the processor that an interrupt of high enough priority is requesting service. bits 0 4 indicate to the proces- sor the type vector of the highest-priority source re- questing service. reading the poll word causes the in-service bit of the highest priority source to be set. it is desirable to be able to read the poll word infor- mation without guaranteeing service of any pending interrupt, i.e., not set the indicated in-service bit. the m80c186 provides a poll status word in addition to the conventional poll word to allow this to be done. poll word information is duplicated in the poll status word, but reading the poll status word does not set the associated in-service bit. these words are locat- ed in two adjacent memory locations in the register file. master mode features programmable priority the user can program the interrupt sources into any of eight different priority levels. the programming is done by placing a 3-bit priority level (0 7) in the con- trol register of each interrupt source. (a source with a priority level of 4 has higher priority over all priority levels from 5 to 7. priority registers containing values lower than 4 have greater priority). all interrupt sources have preprogrammed default priority levels (see table 4). if two requests with the same programmed priority level are pending at once, the priority ordering scheme shown in table 4 is used. if the serviced interrupt routine reenables interrupts, it allows other requests to be serviced. end-of-interrupt command the end-of-interrupt (eoi) command is used by the programmer to reset the in-service (is) bit when an interrupt service routine is completed. the eoi com- mand is issued by writing the proper pattern to the eoi register. there are two types of eoi commands, specific and nonspecific. the nonspecific command does not specify which is bit is reset. when issued, the interrupt controller automatically resets the is bit of the highest priority source with an active service routine. a specific eoi command requires that the programmer send the interrupt vector type to the in- terrupt controller indicating which source's is bit is to be reset. this command is used when the fully nested structure has been disturbed or the highest priority is bit that was set does not belong to the service routine in progress. trigger mode the four external interrupt pins can be programmed in either edge- or level-trigger mode. the control register for each external source has a level-trigger mode (ltm) bit. all interrupt inputs are active high. in the edge sense mode or the level-trigger mode, the interrupt request must remain active (high) until the interrupt request is acknowledged by the 33
m80c186 m80c186 cpu. in the edge-sense mode, if the level remains high after the interrupt is acknowledged, the input is disabled and no further requests will be gen- erated. the input level must go low for at least one clock cycle to reenable the input. in the level-trigger mode, no such provision is made: holding the inter- rupt input high will cause continuous interrupt re- quests. interrupt vectoring the m80c186 interrupt controller will generate in- terrupt vectors for the integrated dma channels and the integrated timers. in addition, the interrupt con- troller will generate interrupt vectors for the external interrupt lines if they are not configured in cascade or special fully nested mode. the interrupt vectors generated are fixed and cannot be changed (see ta- ble 4). interrupt controller registers the interrupt controller register model is shown in figure 24. it contains 15 registers. all registers can both be read or written unless specified otherwise. in-service register this register can be read from or written into. the format is shown in figure 25. it contains the in-serv- ice bit for each of the interrupt sources. the in-serv- ice bit is set to indicate that a source's service rou- tine is in progress. when an in-service bit is set, the interrupt controller will not generate interrupts to the cpu when it receives interrupt requests from devic- es with a lower programmed priority level. the tmr bit is the in-service bit for all three timers; the d0 and d1 bits are the in-service bits for the two dma channels; the i0 i3 are the in-service bits for the external interrupt pins. the is bit is set when the processor acknowledges an interrupt request either by an interrupt acknowledge or by reading the poll register. the is bit is reset at the end of the interrupt service routine by an end-of-interrupt command is- sued by the cpu. interrupt request register the internal interrupt sources have interrupt request bits inside the interrupt controller. the format of this register is shown in figure 25. a read from this regis- ter yields the status of these bits. the tmr bit is the logical or of all timer interrupt requests. d0 and d1 are the interrupt request bits for the dma channels. the state of the external interrupt input pins is also indicated. the state of the external interrupt pins is not a stored condition inside the interrupt controller, therefore the external interrupt bits cannot be writ- ten. the external interrupt request bits show exactly when an interrupt request is given to the interrupt controller, so if edge-triggered mode is selected, the bit in the register will be high only after an inactive- to-active transition. for internal interrupt sources, the register bits are set when a request arrives and are reset when the processor acknowledges the re- quests. writes to the interrupt request register will affect the d0 and d1 interrupt request bits. setting either bit will cause the corresponding interrupt request while clearing either bit will remove the corresponding in- terrupt request. all other bits in the register are read- only. mask register this is a 16-bit register that contains a mask bit for each interrupt source. the format for this register is shown in figure 25. a one in a bit position corre- 270500 12 figure 23. cascade and special fully nested mode interrupt controller connections 34
m80c186 sponding to a particular source serves to mask the source from generating interrupts. these mask bits are the exact same bits which are used in the indi- vidual control registers; programming a mask bit us- ing the mask register will also change this bit in the individual control registers, and vice versa. offset int3 control register 3eh int2 control register 3ch int1 control register 3ah int0 control register 38h dma 1 control register 36h dma 0 control register 34h timer control register 32h interrupt status register 30h interrupt request register 2eh in-service register 2ch priority mask register 2ah mask register 28h poll status register 26h poll register 24h eoi register 22h figure 24. interrupt controller registers (master mode) priority mask register this register is used to mask all interrupts below par- ticular interrupt priority levels. the format of this reg- ister is shown in figure 26. the code in the lower three bits of this register inhibits interrupts of priority lower (a higher priority number) than the code speci- fied. for example, 100 written into this register masks interrupts of level five (101), six (110), and seven (111). the register is reset to seven (111) upon reset so no interrupts are masked due to priority number. interrupt status register this register contains general interrupt controller status information. the format of this register is shown in figure 27. the bits in the status register have the following functions: dhlt: dma halt transfer; setting this bit halts all dma transfers. it is automatically set when- ever a non-maskable interrupt occurs, and it is reset when an iret instruction is execut- ed. the purpose of this bit is to allow prompt service of all non-maskable interrupts. this bit may also be set by the programmer. irtx: these three bits represent the individual tim- er interrupt request bits. these bits are used to differentiate the timer interrupts, since the timer ir bit in the interrupt request register is the ``or'' function of all timer interrupt re- quest. note that setting any one of these three bits initiates an interrupt request to the interrupt controller. 1514 109876543210 00 ### 0 0 0 13 12 i1 i0 d1 d0 0 tmr figure 25. in-service, interrupt request, and mask register formats 15 14 3210 00 ######### 0 prm2 prm1 prm0 figure 26. priority mask register format 1514 76543210 dhlt 0 ##### 00000 irt2 irt1 irt0 figure 27. interrupt status register format (master mode) 35
m80c186 timer, dma 0, 1; control register these registers are the control words for all the in- ternal interrupt sources. the format for these regis- ters is shown in figure 28. the three bit positions pr0, pr1, and pr2 represent the programmable pri- ority level of the interrupt source. the msk bit inhib- its interrupt requests from the interrupt source. the msk bits in the individual control registers are the exact same bits as are in the mask register; modify- ing them in the individual control registers will also modify them in the mask register, and vice versa. int0-int3 control registers these registers are the control words for the four external input pins. figure 29 shows the format of the int0 and int1 control registers; figure 30 shows the format of the int2 and int3 control reg- isters. in cascade mode or special fully nested mode, the control words for int2 and int3 are not used. the bits in the various control registers are encoded as follows: pro-2: priority programming information. highest priority e 000, lowest priority e 111 ltm: level-trigger mode bit. 1 e level-triggered; 0 e edge-triggered. interrupt input levels are active high. in level-triggered mode, an interrupt is generated whenever the exter- nal line is high. in edge-triggered mode, an interrupt will be generated only when this level is preceded by an inactive-to-active transition on the line. in both cases, the level must remain active until the interrupt is acknowledged. msk: mask bit, 1 e mask; 0 e non-mask. c: cascade mode bit, 1 e cascade; 0 e di- rect sfnm: special fully nested mode bit, 1 e sfnm eoi register the end of the interrupt register is a command regis- ter which can only be written into. the format of this register is shown in figure 30. it initiates an eoi command when written to by the m80c186 cpu. the bits in the eoi register are encoded as follows: s x : encoded information that specifies an in- terrupt source vector type as shown in ta- ble 4. for example, to reset the in-service bit for dma channel 0, these bits should be set to 01010, since the vector type for dma channel 0 is 10. note: to reset the single in-service bit for any of the three timers, the vector type for timer 0 (8) should be written in this register. nspec/: a bit that determines the type of eoi com- spec mand. nonspecific e 1, specific e 0. 1514 43210 00 ######## 0 msk pr2 pr1 pr0 figure 28. timer/dma control registers formats 1514 76543210 00 ##### 0 sfnm c ltm msk pr2 pr1 pr0 figure 29. int0/int1 control register formats 1514 543210 00 ####### 0 ltm msk pr2 pr1 pr0 figure 30. int2/int3 control register formats 36
m80c186 poll and poll status registers these registers contain polling information. the for- mat of these registers is shown in figure 32. they can only be read. reading the poll register consti- tutes a software poll. this will set the is bit of the highest priority pending interrupt. reading the poll status register will not set the is bit of the highest priority pending interrupt; only the status of pending interrupts will be provided. encoding of the poll and poll status register bits are as follows: s x : encoded information that indicates the vector type of the highest priority inter- rupting source. valid only when intreq e 1. intreq: this bit determines if an interrupt request is present. interrupt request e 1; no in- terrupt request e 0. slave mode operation when slave mode is used, the internal m80c186 in- terrupt controller will be used as a slave controller to an external master interrupt controller. the internal m80c186 resources will be monitored by the internal interrupt controller, while the external controller functions as the system master interrupt controller. upon reset, the m80c186 will be in master mode. to provide for slave mode operation bit 14 of the relo- cation register should be set. because of pin limitations caused by the need to interface to an external m82c59a master, the inter- nal interrupt controller will no longer accept external inputs. there are however, enough m80c186 inter- rupt controller inputs (internally) to dedicate one to each timer. in this mode, each timer interrupt source has its own mask bit, is bit, and control word. in slave mode each peripheral must be assigned a unique priority to ensure proper interrupt controller operation. therefore, it is the programmer's respon- sibility to assign correct priorities and initialize inter- rupt control registers before enabling interrupts. slave mode external interface the configuration of the m80c186 with respect to an external m82c59a master is shown in figure 33. the int0 (pin 45) input is used as the m80c186 cpu interrupt input. int3 (pin 41) functions as an output to send the m80c186 slave-interrupt-request to one of the 8 master-pic-inputs. 15 14 13 5 4 3 2 1 0 spec/ 00 ####### 0 s4s3s2s1s0 nspec figure 31. eoi register format 151413 543210 int 00 ####### 0 s4s3s2s1s0 req figure 32. poll and poll status register format 37
m80c186 270500 13 figure 33. slave mode interrupt controller connections correct master-slave interface requires decoding of the slave addresses (cas0-2). slave m82c59as do this internally. because of pin limitations, the m80c186 slave address will have to be decoded ex- ternally. int1 (pin 44) is used as a slave-select in- put. note that the slave vector address is transferred internally, but the ready input must be supplied ex- ternally. int2 (pin 42) is used as an acknowledge output, suitable to drive the inta input of an m82c59a. interrupt nesting slave mode operation allows nesting of interrupt re- quests. when an interrupt is acknowledged, the pri- ority logic masks off all priority levels except those with equal or higher priority. vector generation in the slave mode vector generation in slave mode is exactly like that of an m82c59a slave. the interrupt controller gen- erates an 8-bit vector which the cpu multiplies by four and uses as an address into a vector table. the significant five bits of the vector are user-program- mable while the lower three bits are generated by the priority logic. these bits represent the encoding of the priority level requesting service. the signifi- cant five bits of the vector are programmed by writ- ing to the interrupt vector register at offset 20h. specific end-of-interrupt in slave mode the specific eoi command operates to reset an in-service bit of a specific priority. the user supplies a 3-bit priority-level value that points to an in-service bit to be reset. the command is exe- cuted by writing the correct value in the specific eoi register at offset 22h. interrupt controller registers in the slave mode all control and command registers are located inside the internal peripheral control block. figure 34 shows the offsets of these registers. end-of-interrupt register the end-of-interrupt register is a command register which can only be written. the format of this register is shown in figure 35. it initiates an eoi command when written by the m80c186 cpu. the bits in the eoi register are encoded as follows: l x : encoded value indicating the priority of the is bit to be reset. 38
m80c186 in-service register this register can be read from or written into. it con- tains the in-service bit for each of the internal inter- rupt sources. the format for this register is shown in figure 36. bit positions 2 and 3 correspond to the dma channels; positions 0, 4, and 5 correspond to the integral timers. the source's is bit is set when the processor acknowledges its interrupt request. interrupt request register this register indicates which internal peripherals have interrupt requests pending. the format of this register is shown in figure 36. the interrupt request bits are set when a request arrives from an internal source, and are reset when the processor acknowl- edges the request. as in master mode, d0 and d1 are read/write; all other bits are read only. mask register the register contains a mask bit for each interrupt source. the format for this register is shown in fig- ure 36. if the bit in this register corresponding to a particular interrupt source is set, any interrupts from that source will be masked. these mask bits are ex- actly the same bits which are used in the individual control registers, i.e., changing the state of a mask bit in this register will also change the state of the mask bit in the individual interrupt control register corresponding to the bit. control registers these registers are the control words for all the in- ternal interrupt sources. the format of these regis- ters is shown in figure 37. each of the timers and both of the dma channels have their own control register. the bits of the control registers are encoded as follows: pr x : 3-bit encoded field indicating a priority level for the source; note that each source must be programmed at specified levels. msk: mask bit for the priority level indicated by pr x bits. offset level 5 control register 3ah (timer 2) level 4 control register 38h (timer 1) level 3 control register 36h (dma 1) level 2 control register 34h (dma 0) level 0 control register 32h (timer 0) interrupt status register 30h interrupt-request register 2eh in-service register 2ch priority-level mask register 2ah mask register 28h specific eoi register 22h interrupt vector register 20h figure 34. interrupt controller registers (slave mode) 151413 876543210 000 #### 000000l2l1l0 figure 35. specific eoi register format 15 14 13 8 7 6 5 4 3 2 1 0 000 #### 0 0 0 tmr2 tmr1 d1 d0 0 tmr0 figure 36. in-service, interrupt request, and mask register format 39
m80c186 interrupt vector register this register provides the upper five bits of the inter- rupt vector address. the format of this register is shown in figure 38. the interrupt controller itself provides the lower three bits of the interrupt vector as determined by the priority level of the interrupt request. the format of the bits in this register is: t x : 5-bit field indicating the upper five bits of the vector address. priority-level mask register this register indicates the lowest priority-level inter- rupt which will be serviced. the encoding of the bits in this register is: m x : 3-bit encoded field indication priority-level val- ue. all levels of lower priority will be masked. interrupt status register this register is defined as in master mode except that dhlt is not implemented (see figure 27). interrupt controller and reset upon reset, the interrupt controller will perform the following actions: # all sfnm bits reset to 0, implying fully nested mode. # all pr bits in the various control registers set to 1. this places all sources at lowest priority (level 111). # all ltm bits reset to 0, resulting in edge-sense mode. # all interrupt service bits reset to 0. # all interrupt request bits reset to 0. # all msk (interrupt mask) bits set to 1 (mask). # all c (cascade) bits reset to 0 (non-cascade). # all prm (priority mask) bits set to 1, implying no levels masked. # initialized to master mode. 151413 876543210 000 #### 00000mskpr2pr1pr0 figure 37. control word format 151413 876543210 000 #### 0 t4t3t2t1t0 0 0 0 figure 38. interrupt vector register format 151413 876543210 000 #### 000000m2m1m0 figure 39. priority level mask register 40
m80c186 enhanced mode operation in enhanced mode, the m80c186 will operate with power-save, dram refresh, and numerics coproc- essor support in addition to all the compatible mode features. in compatible mode the m80c186 operates with all the features of the nmos m80186, with the excep- tion of m8087 support (i.e. no numeric coprocessing is possible in compatible mode). queue-status in- formation is still available for design purposes other than m8087 support. all the enhanced mode features are completely masked when in compatible mode. a write to any of the enhanced mode registers will have no effect, while a read will not return any valid data. entering enhanced mode if connected to a numerics coprocessor, this mode will be invoked automatically. without a npx, this mode can be entered by tying the reset output signal from the m80c186 to the test/busy input. queue-status mode the queue-status mode is entered by strapping the rd pin low. rd is sampled at reset and if low, the m80c186 will reconfigure the ale and wr pins to be qs0 and qs1 respectively. this mode is avail- able on the m80c186 in both compatible and en- hanced modes and is identical to the nmos m80186. dram refresh control unit description the refresh control unit (rcu) automatically gen- erates dram refresh bus cycles. the rcu operates only in enhanced mode. after a programmable peri- od of time, the rcu generates a memory read re- quest to the biu. if the address generated during a refresh bus cycle is within the range of a properly programmed chip select, that chip select will be acti- vated when the biu executes the refresh bus cycle. the ready logic and wait states programmed for that region will also be in force. if no chip select is acti- vated, then external ready is automatically required to terminate the refresh bus cycle. if the hlda pin is active when a dram refresh re- quest is generated (indicating a bus hold condition), then the m80c186 will deactivate the hlda pin in order to perform a refresh cycle. the circuit external to the m80c186 must remove the hold signal in order to execute the refresh cycle. the sequence of hlda going inactive while hold is being held active can be used to signal a pending refresh request. all registers controlling dram refresh may be read and written in enhanced mode. when the processor is operating in compatible mode, they are deselect- ed and are therefore inaccessible. some fields of these registers cannot be written and are always read as zeros. dram refresh addresses the address generated during a refresh cycle is de- termined by the contents of the mdram register (see figure 40) and the contents of a 9-bit counter. figure 41 illustrates the origin of each bit. 1514131211109876543210 mdram: m6 m5 m4 m3 m2 m1 m0 000000000 offset e0h bits 0 8: reserved, read back as 0. bits 9 15: m0 m6, are address bits a13 a19 of the 20-bit memory refresh address. these bits should correspond to the chip select address to be activated for the dram partition. these bits are set to 0 on reset. figure 40. memory partition register a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 m6 m5 m4 m3 m2 m1 m0 0 0 0 ca8 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 1 m6 m0: bits defined by mdram register ca8 ca0: bits defined by refresh address counter figure 41. addresses generated by rcu 41
m80c186 1514131211109876543210 cdram: 0000000c8c7c6c5c4c3c2c1c0 offset e2h bits 0 8: c0 c8, clock divisor register, holds the number of clkout cycles between each refresh request. bits 9 15: reserved, read back as 0. figure 42. clock pre-scaler register 1514131211109876543210 edram: e 000000t8t7t6t5t4t3t2t1t0 offset e4h bits 0 8: t0 t8, refresh clock counter outputs. read only. bits 9 14: reserved, read back as 0. bit 15: enable rcu, set to 0 on reset. figure 43. enable rcu register refresh control unit programming and operation after programming the mdram and the cdram registers (figures 40 and 42), the rcu is enabled by setting the ``e'' bit in the edram register (figure 43). the clock counter (t0 t8 of edram) will be loaded from c0 c8 of cdram during t 3 of instruc- tion cycle that sets the ``e'' bit. the clock counter is then decremented at each subsequent clkout. a refresh is requested when the value of the counter has reached 1 and the counter is reloaded from cdram. in order to avoid missing refresh requests, the value in the cdram register should always be at least 18 (12h). clearing the ``e'' bit at anytime will clear the counter and stop refresh requests, but will not reset the refresh address counter. power-save control power save operation the m80c186, when in enhanced mode, can enter a power saving state by internally dividing the clock- in frequency by a programmable factor. this divided frequency is also available at the clkout pin. the pdcon register contains the two-bit fields for se- lecting the clock division factor and the enable bit. all internal logic, including the refresh control unit and the timers, will have their clocks slowed down by the division factor. to maintain a real time count or a fixed dram refresh rate, these peripherals must be re-programmed when entering and leaving the power-save mode. the power-save mode is exited whenever an inter- rupt is processed by automatically resetting the en- able bit. if the power-save mode is to be re-entered after serving the interrupt, the enable bit will need to be reset in software before returning from the inter- rupt routine. the internal clocks of the m80c186 will begin to be divided during the t 3 state of the instruction cycle that sets the enable bit. clearing the enable bit will restore full speed in the t 3 state of that instruction. at no time should the internal clock frequency be allowed to fall below 0.5 mhz. this is the minimum operational frequency of the m80c186. for exam- ple, an m80c186 running with a 12 mhz crystal (6 mhz clockout) should never have a clock divi- sor greater than eight. 42
m80c186 1514131211109876543210 pdcon: e 0 0 0 0 0 0 0000000f1f0 offset f0h bits 0 1: clock divisor select f1 f0 division factor 0 0 divide by 1 0 1 divide by 4 1 0 divide by 8 1 1 divide by 16 bits 2 14: reserved, read back as zero. bit 15: enable power save mode. set to zero on reset. figure 44. power-save control register numeric coprocessor (npx) extension three of the mid-range memory chip selects are re- defined according to table 16 when using the nu- merics coprocessor extension. the fourth chip se- lect, mcs2 functions as in compatible mode, and may be programmed for activity with ready logic and wait states accordingly. as in compatible mode, mcs2 will function for one-fourth a programmed block size. table 16. mcs assignments compatible enhanced mode mode mcs0 pereq processor extension request mcs1 error npx error mcs2 mcs2 mid-range chip select mcs3 nps numeric processor select four port addresses are assigned to the npx for 16- bit reads and writes by the m80c186. table 17 shows the port definitions. these ports are not ac- cessible by using the m80c186 i/o instructions. however, numerics operations will cause a pcs line to be activated if it is properly programmed for this i/o range. table 17. numerics coprocessor i/o port assignments i/o address read definition write definition 00f8h status/control opcode 00fah data data 00fch reserved cs:ip, ds:ea 00feh opcode status reserved ``once'' test mode to facilitate testing and inspection of devices when fixed into a target system, the m80c186 has a test mode available which allows all pins to be placed in a high-impedance state. ``once'' stands for ``on circuit emulation''. when placed in this mode, the m80c186 will put all pins in the high-impedance state until reset. the once mode is selected by tying the ucs and the lcs low during reset. these pins are sam- pled on the low-to-high transition of the res pin. the ucs and the lcs pins have weak internal pull- up resistors similar to the rd and test /busy pins to guarantee proper normal operation. 43
m80c186 absolute maximum ratings * case temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 1.0v to a 7.0v package power dissipation 1w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions mil-std-883 symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v military temperature only (mto) symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v dc characteristics (over specified operating conditions) symbol parameter min max units comments v il input low voltage b 0.5 0.2 v cc b 0.3 v v ih input high voltage 0.2 v cc a 1.1 v cc v (all except x1 and res ) v ih1 input high voltage (res ) 3.0 v cc v v ih2 input high voltage 0.2 v cc a 1.3 v cc v (ardy/srdy) v ol output low voltage 0.45 v i ol e 2.5 ma (s0, 1, 2) i ol e 2.0 ma (others) v oh output high voltage 2.4 v cc vi oh eb 2.4 ma @ 2.4v (4) 0.8 v cc v cc vi oh eb 200 m a @ 0.8 v cc (4) i cc power supply current 160 ma 12.5 mhz (3) 140 ma 10 mhz (3) i ps power save current 10 ma per mhz a 20 ma typical @ 25 c, v cc e 5.0v i li input leakage current g 10 m a 0.45v s v in s v cc i lo output leakage current g 10 m a 0.45v s v out s v cc (1) v clo clock output low 0.5 v i clo e 4.0 ma v cho clock output high 0.8 v cc vi cho eb 500 m a notes: 1. pins being floated during hold or by invoking the once mode. 2. characterization conditions are a) frequency e 1 mhz; b) unmeasured pins at gnd; v in at a 5.0v or a 0.45v. 3. current is measured with the device in reset with x1 and x2 driven and all other non-power pins open. 4. rd /qsmd , ucs , msc0 /pereq, mcsl /error , and test /busy pins have internal pullup devices that are active at reset. excessive loading on these pins can cause the m80c186 to go into undesired modes of operation (e.g., queue status, once) upon reset. 44
m80c186 dc characteristics (over specified operating conditions) (continued) symbol parameter min max units comments v cli clock input low voltage (x1) b 0.5 0.6 v v chi clock input high voltage (x1) 3.9 v cc v c in input capacitance 10 pf @ 1 mhz (2) c io i/o capacitance 20 pf @ 1 mhz (2) notes: 1. pins being floated during hold or by invoking the once mode. 2. characterization conditions are a) frequency e 1 mhz; b) unmeasured pins at gnd; v in at a 5.0v or a 0.45v. 3. current is measured with the device in reset with x1 and x2 driven and all other non-power pins open. 4. rd /qsmd , ucs , msc0 /pereq, mcsl /error , and test /busy pins have internal pullup devices that are active at reset. excessive loading on these pins can cause the m80c186 to go into undesired modes of operation (e.g., queue status, once) upon reset. pin timings ac characteristics (over specified operating conditions) all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 200 pf (10 mhz) and c l e 50 100 pf (12.5 mhz). for ac tests, input v il e 0.45v and v in e 2.4v except at x 1 where v ih e v cc b 0.5v. symbol parameter m80c186-10 m80c186-12 unit comments min max min max m80c186 timing requirements t dvcl data in setup (a/d) 20 20 ns t cldx data in hold (a/d) 5 5 ns t arych ardy resolution 20 20 ns transition setup time (1) t arylcl asynchronous ready 30 30 ns (ardy) setup time t clarx ardy active hold time 15 15 ns t arychl ardy inactive hold time 15 15 ns t srycl synchronous ready (srdy) 20 20 ns transition setup time t clsry srdy transition hold time 20 20 ns t hvcl hold setup (1) 20 20 ns t invch intr, nmi, test, tmr in 20 20 ns setup time (1) t invcl drq0, drq1, setup time (1) 20 20 ns m80c186 master interface timing responses t clav address valid delay 5 50 5 37 ns c l e t clax address hold 0 0 ns 50 pf 200 pf t claz address float delay t clax 30 t clax 25 ns all outputs (except t cltmv ) t chcz command lines float delay 40 33 ns @ 10 mhz t chcv command lines valid 45 37 ns delay (after float) c l e t lhll ale width (min) t clcl b 30 t clcl b 30 ns 50 pf 100 pf all outputs t chlh ale active delay 30 25 ns @ 12.5 mhz t chll ale inactive delay 30 25 ns 45
m80c186 pin timings (continued) ac characteristics (over specified operating conditions) (continued) all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 200 pf (10 mhz) and c l e 50 100 pf (12.5 mhz). for ac tests, input v il e 0.45v and v in e 2.4v except at x 1 where v ih e v cc b 0.5v. symbol parameter m80c186-10 m80c186-12 unit comments min max min max m80c186 master interface timing responses (continued) t llax address hold to t chcl b 20 t chcl 15 ns 50 pf 100 pf @ 10 mhz all outputs c l e (except t cltmv) 50 pf 200 pf b @ 12.5 mhz c l e all outputs ale inactive (min) t cldv data valid delay 5 40 5 36 ns t cldox data hold time 3 3 ns t whdx data hold after wr (min) t clcl b 34 t clcl b 20 ns t cvctv control active delay 1 3 56 3 47 ns t chctv control active delay 2 5 44 5 37 ns t cvctx control inactive delay 4 44 5 37 ns t cvdex den inactive delay 5 56 5 47 ns (non-write cycle) t azrl address float to 0 0 ns rd active t clrl rd active delay 5 44 5 37 ns t clrh rd inactive delay 5 44 5 37 ns t rhlh rd inactive to ale high t clch b 14 t clch b 14 ns t rhav rd inactive to t clcl b 40 t clcl b 20 ns address active (min) t clhav hlda valid delay 5 40 4 33 ns t rlrh rd pulse width (min) 2t clcl b 46 2t clcl b 40 ns t rvch rd valid to 25 25 ns clock high t wlwh wr pulse width (min) 2t clcl b 34 2t clcl b 30 ns t whlh wr inactive to aee high t clch b 14 t clch b 14 ns t whdex wr inactive to t clch b 10 t clch b 10 ns den inactive t csvll chip select valid t clch b 14 t clch b 14 ns to ale low t avll address valid to t clch b 19 t clch b 15 ns ale low (min) t chsv status active delay 5 45 5 35 ns t clsh status inactive delay 5 50 5 35 ns t cltmv timer output delay 48 40 ns 100 pf max @ 10 mhz 46
m80c186 ac characteristics (over specified operating conditions) (continued) all timings are measured at 1.5v and 100 pf loading on clkout unless otherwise noted. all output test conditions are with c l e 50 200 pf (10 mhz) and c l e 50 100 pf (12.5 mhz). for ac tests, input v il e 0.45v and v in e 2.4v except at x 1 where v ih e v cc b 0.5v. symbol parameter m80c186-10 m80c186-12 unit comments min max min max m80c186 master interface timing responses (continued) t clro reset delay 48 40 ns c l e 50 200 pf t chqsv queue status delay 28 28 ns all outputs t chdx status hold time 5 5 ns (except t cltmv ) t avch address valid to 0 0 c l e 50 100 pf @ 10 mhz clock high all outputs t cllv lock valid/invalid 5 45 5 40 ns @ 12.5 mhz delay t dxdl den inactive to 0 0 ns dt/r low m80c186 chip-select timing responses t clcsv chip-select 45 33 ns active delay t cxcsx chip-select hold from t clch b 10 t clch b 10 ns command inactive t chcsx chip-select 5 40 5 36 ns inactive delay m80c186 clkin requirements measurements taken with following conditions: external clock input to x1 and x2 not connected (float) t ckin clkin period 50 1000 40 1000 ns t ckhl clkin fall time 5 5 ns 3.5 to 1.0v (1) t cklh clkin rise time 5 5 ns 1.0 to 3.5v (1) t clck clkin low time 23 18 ns 1.5v (2) t chck clkin high time 23 18 ns 1.5v (2) m80c186 clkout timing 200 pf load maximum for 10 mhz or less t cico clkin to 25 21 ns clkout skew t clcl clkout period 100 2000 80 2000 ns t clch clkout 0.5 t clcl b 8 0.5 t clcl b 7 ns 1.5v low time (min) t chcl clkout 0.5 t clcl b 8 0.5 t clcl b 7 ns 1.5v high time (min) t ch1ch2 clkout rise time 10 10 ns 1.0 to 3.5v t cl2cl1 clkout fall time 10 10 ns 3.5 to 1.0v note: 1. these values are supplied for design purposes. 2. t clck and t chck (clkin low and high times) should not have a duration less than 45% of t ckin . 47
m80c186 waveforms major cycle timing 270500 16 48
m80c186 waveforms (continued) major cycle timing (continued) 270500 17 notes: 1. the data hold time last only until inta goes inactive, even if the inta transition occurs prior to t cldx (min). 2. inta occurs one clock later in slave mode. 3. status inactive just prior to t 4 . 4. latched a1 and a2 have the same timings as pcs5 and pcs6 . 5. for write cycle followed by read. 49
m80c186 waveforms (continued) 270500 18 270500 32 50
m80c186 waveforms (continued) ready timing 270500 23 hold-hlda timing 270500 20 51
m80c186 waveforms (continued) timer on m80c186 270500 21 52
m80c186 waveforms (continued) typical output delay capacitive derating 270500 33 figure 45. capacitive derating curve m80c186 execution timings a determination of m80c186 program execution tim- ing must consider both the bus cycles necessary to prefetch instructions as well as the number of exe- cution unit cycles necessary to execute instructions. the following instruction timings represent the mini- mum execution time in clock cycles for each instruc- tion. the timings given are based on the following assumptions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries. all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the biu and execution unit. with a 16-bit biu, the m80c186 has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue most of the time. therefore, actual program execution will not be substantially greater than that derived from adding the instruction timings shown. 53
m80c186 instruction set summary function format clock comments cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 register/memory to register 1000101w modreg r/m 2/9 immediate to register/memory 1100011w mod000 r/m data data if w e 1 12 13 8/16-bit immediate to register 1011w reg data data if w e 1 3 4 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 accumulator to memory 1010001w addr-low addr-high 9 register/memory to segment register 10001110 mod0reg r/m 2/9 segment register to register/memory 10001100 mod0reg r/m 2/11 push e push: memory 11111111 mod110 r/m 16 register 01010 reg 10 segment register 000reg110 9 immediate 011010s0 data data if s e 010 pusha e push all 01100000 36 pop e pop: memory 10001111 mod000 r/m 20 register 01011 reg 10 segment register 000reg111 (reg i 01) 8 popa e popall 01100001 51 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 register with accumulator 10010 reg 3 in e input from: fixed port 1110010w port 10 variable port 1110110w 8 out e output to: fixed port 1110011w port 9 variable port 1110111w 7 xlat e translate byte to al 11010111 11 lea e load ea to register 10001101 modreg r/m 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 lahf e load ah with flags 10011111 2 sahf e store ah into flags 10011110 3 pushf e push flags 10011100 9 popf e pop flags 10011101 8 shaded areas indicate instructions not available in m8086, m8088 microsystems. 54
m80c186 instruction set summary (continued) function format clock comments cycles data transfer (continued) segment e segment override: cs 00101110 2 ss 00110110 2 ds 00111110 2 es 00100110 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 immediate to accumulator 0000010w data data if w e 1 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 immediate to accumulator 0001010w data data if w e 1 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 register 01000 reg 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 immediate from accumulator 0010110w data data if w e 1 3/4 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 immediate from accumulator 0001110w data data if w e 1 3/4 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 register 01001 reg 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 register with register/memory 0011100w modreg r/m 3/10 immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 immediate with accumulator 0011110w data data if w e 1 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 aaa e ascii adjust for add 00110111 8 daa e decimal adjust for add 00100111 4 aas e ascii adjust for subtract 00111111 7 das e decimal adjust for subtract 00101111 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 register-word 3537 memory-byte 3234 memory-word 4143 shaded areas indicate instructions not available in m8086, m8088 microsystems. 55
m80c186 instruction set summary (continued) function format clock comments cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 register-word 3437 memory-byte 3134 memory-word 4043 imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 22 25/ (signed) 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 register-word 38 memory-byte 35 memory-word 44 idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 register-word 5361 memory-byte 5058 memory-word 5967 aam e ascii adjust for multiply 11010100 00001010 19 aad e ascii adjust for divide 11010101 00001010 15 cbw e convert byte to word 10011000 2 cwd e convert word to double word 10011001 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 immediate to accumulator 0010010w data data if w e 1 3/4 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 immediate data and accumulator 1010100w data data if w e 1 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 immediate to accumulator 0000110w data data if w e 1 3/4 8/16-bit shaded areas indicate instructions not available in m8086, m8088 microsystems. 56
m80c186 instruction set summary (continued) function format clock comments cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 immediate to accumulator 0011010w data data if w e 1 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 string manipulation movs e move byte/word 1010010w 14 cmps e compare byte/word 1010011w 22 scas e scan byte/word 1010111w 15 lods e load byte/wd to alax 1010110w 12 stos e stor byte/wd from ala 1010101w 10 ins e input byte/wd from dx port 0110110w 14 outs e output byte/wd to dx port 0110111w 14 repeated by count in cx movs e move string 11110010 1010010w 8 a 8n cmps e compare string 1111001z 1010011w 5 a 22n scas e scan string 1111001z 1010111w 5 a 15n lods e load string 11110010 1010110w 6 a 11n stos e store string 11110010 1010101w 6 a 9n ins e input string 11110010 0110110w 8 a 8n outs e output string 11110010 0110111w 8 a 8n control transfer call e call: direct within segment 11101000 disp-low disp-high 15 register/memory 11111111 mod010 r/m 13/19 indirect within segment direct intersegment 10011010 segment offset 23 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 jmp e unconditional jump: short/long 11101011 disp-low 14 direct within segment 11101001 disp-low disp-high 14 register/memory 11111111 mod100 r/m 11/17 indirect within segment direct intersegment 11101010 segment offset 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 shaded areas indicate instructions not available in m8086, m8088 microsystems. 57
m80c186 instruction set summary (continued) function format clock comments cycles control transfer (continued) ret e return from call: within segment 11000011 16 within seg adding immed to sp 11000010 data-low data-high 18 intersegment 11001011 22 intersegment adding immediate to sp 11001010 data-low data-high 25 je/jz e jump on equal/zero 01110100 disp 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 jo e jump on overflow 01110 000 disp 4/13 js e jump on sign 01111000 disp 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 jno e jump on not overflow 01110001 disp 4/13 jns e jump on not sign 01111001 disp 4/13 jcxz e jump on cx zero 11100011 disp 5/15 loop e loop cx times 11100010 disp 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 l e 1 25 l l 1 22 a 16(n b 1) leave e leave procedure 11001001 8 int e interrupt: type specified 11001101 type 47 type 3 11001100 45 if int. taken/ into e interrupt on overflow 11001110 48/4 if int. not taken iret e interrupt return 11001111 28 bound e detect value out of range 01100010 modreg r/m 3335 shaded areas indicate instructions not available in m8086, m8088 microsystems. 58
m80c186 instruction set summary (continued) function format clock comments cycles processor control clc e clear carry 11111000 2 cmc e complement carry 11110101 2 stc e set carry 11111001 2 cld e clear direction 11111100 2 std e set direction 11111101 2 cli e clear interrupt 11111010 2 sti e set interrupt 11111011 2 hlt e halt 11110100 2 wait e wait 10011011 6 if test e 0 lock e bus lock prefix 11110000 2 esc e processor extension escape 11011ttt modlll r/m 6 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in m8086, m8088 microsystems. footnotes the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a reg field if mod e 00 then disp e 0 * , disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. 59

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